The verilog netlist contains more than 40 thousands component. When I import the netlist into cadence, it gives me an error of "Illegal bus reference - Can't tap "Neta" from "Netb".". I looked through the generated schematic, it messed up Neta and Netb. I cheked the Schematic Generation Options befoe importing the netlist again. The Maximum number of Rows/columns are limited to 1024. Is it possible to increase the Maximum Number of Rows/Columns of the schmatic before importing the large netlist?
I suggest you contact customer support. You didn't say which version you're using - which is quite important as there have been a number of fixes related to Verilogin.
You could always turn off the Full Place & Route option, so that it doesn't attempt to fully route the schematic. You could also decrease the density - it's a slider on the form. But without knowing what the real issue, it's hard to be sure. 1024x1024 should be OK for 40k components.
If you turn off the "full place and route" option, it will generate the schematic only containing components. That's solved the the problem.