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Skill function to create Verilog-Header file by export from "symbol"

PTRV

Hello,

I am looking for a solution for the following task: creating 2 Verilog-Header files (with and without power/ground pins) out of the Symbol view.

Can you perhaps help me with this?

Best Regards

 

Parents
  • Li Ting

    The public SKILL functions schSymbolToPinList and schPinListToVerilog should give you most of what you want.
    If your symbol already contains the power/ground pins then you can post process the return from schSymbolToPinList to strip out these terminals.
     
     
Reply
  • Li Ting

    The public SKILL functions schSymbolToPinList and schPinListToVerilog should give you most of what you want.
    If your symbol already contains the power/ground pins then you can post process the return from schSymbolToPinList to strip out these terminals.
     
     
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