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Find a list of floating gates in schematic

pham777

Hi,

I wonder if there is a skill code to find hierarchily a list of transistors which have its gate

1) not connected to power/ground

2) and not connected to other devices(transistors, R,L,C)

I am using cadence IC615.

Thanks a lot,

HP

  • Hi HP

    I think it can be done by examining the net info of each transistor hierarchically. But this is an ERC (Electrical Rule Check) problem which should be resolved using an LVS tool. Using SKILL is definitely not the most efficient approach. The problem can be resolved using Assura or PVS as follows:

    === Assura ===
    ercPathCheck(noPwr or noGnd "No pwr/gnd connection")
    ercCheckFloatingDevices(mosSourceOrDrain)

    === PVS ===
    erc_pathcheck -power not -or -ground not
    lvs_filter_option AE
    lvs_report_option -filtered_devices

    Check "design.cfr" file in the PVS LVS run directory for a list of floating mos devices which have been filtered.


    Best regards
    Quek

  • Hi Quek,

    Thanks for your input. Yes, DRC rule deck (not ERC) can catch these floating gates, but it only happen when you run DRC at the top level ( analog + digital ). At that time, it's probably too late .... The situation is this:

    we work on analog section of the chip and deliver to PnR people who will integrate with digital section. We see a lot of floating gates at our analog section but we don't know if they are real or not at this stage. What happen is there are a lot of gates which connected to output/input pins which inturn will be connected to digital section. Some of them are unused which cause real floating gates when they run drc at top level.

    I'd like to have a skill code to find a list of transistors in schematic (not in layout) which have its gates not connected to anything except pins, then I can determine which one is not used and terminate it properly by connecting to power/ground.

    Thanks a lot,

    HP

  • This is also something that can be done with a FastSPICE simulator, such as XPS or UltraSim. See "spectre -h static_highz" for more details, and also there's the "dyn_floatdcpath" check which is available in APS (so not a FastSPICE engine) as well as XPS which performs a "Dynamic Floating Node Induced DC Leakage Path Check".

    There's a RAK (Rapid Adoption Kit) for "Static and Dynamic Checks" available here.

    Andrew.


     

  • I would like to check for floating nodes in a top level mixed signal design APS simulation. I am interested in setting the "dyn_floatdcpath" check. Could you possibly help me by letting me know how to set that in ADE?
  • In IC617 there's the checks and asserts assistant. There's a Rapid Adoption Kit (Resources->Rapid Adoption Kits->Custom and Signoff) called "Check & Assertions in Virtuoso ADE XL, Virtuoso ADE Assembler and Virtuoso ADE Explorer" on support.cadence.com which covers this. In IC616 you have to set it up by putting the dyn_floatdcpath statement in an include file.

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