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netlist formatter for spectre and AMS

Jorg

Hi Andrew,

I pray you'll find this and find the time to respond.

I want to write netlist formatters to be used with spectre and amsdesigner (different formatters for different simulators, of course).

What I found in the documentation is, how to integrate a new simulator, which seems to be meant for non-Cadence products.  In my case, it seems a overkill, since I do want to simulate with spectre, later maybe with amsdesigner.

The whole idea evolves around this problem: the electro-analogous systems, that I want to design, use signals which are single connections physically and bussed signals for simulation. For consistency, I want just one set of schematics and create appropriate netlists for simulation and physical verification from them.  Preferrably, the schematics would represent connections as single ports. Thus my idea to customize netlisting for spectre.

Could you please comment on where to best place the resolution of single vs bus for my purpose, and point me someplace how to start the netlist customization?

I also have looked at the netlist procedure property, that can be attached to a cell. This enables me, to manipulate how instances of this particular cell are printed into the netlist of a schematic. However, it leaves me with the problem, how to also manipulate the interface of this schematic netlist, i.e. the subckt/module definition.  Is there a similarily simple way to modify these as well?

 Thank you in advace for any hint and help.

Kind Regards,

Jörg

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  • Andrew Beckett

    Hi Jorg,

    Finally I have had a chance to read all this and reply (sorry it's taken me so long).

    If it had been a single potential and flow, you could have just defined a new discipline and then implemented your model that way. The fact that you want multiple solvants complicates matters.

    One possibility might be to use SystemVerilog and then User Defined Records which allow you to associate multiple real numbers with a port and transfer these between blocks. You'd have to use a signal flow approach rather than a conserved system (i.e. continuous in value, but discrete in time), but it would then allow you to transfer these complex signals between blocks without changing how the interfaces or wires are described. You could also VHDL models rather than SystemVerilog as these offer the same kind of construct.

    Changing the netlister to convert single wires to busses is quite tricky. There are two approaches to AMS netlisting; one of these is the "Cell-Based Netlister", and that's the document you've probably seen. The issue is that this is being deprecated in flavour of an OSS-based netlister (the latest version of this is known as UNL, or Unified Netlister, which addresses most of the shortcomings and implementation issues of the previous OSS-based netlister).

    The CBN approach required you to develop custom netlist procedures (if needed) for special things which were specific to AMS, and also have specific CDF entries for AMS. The OSS/UNL approach requires you to only customize for spectre (CDF and netlist procedures) and then the spectre syntax gets translated into Verilog-AMS syntax. This is for ease of maintenance, primarily.

    Typically all you can customize is how an individual instance is netlisted (and usually this is just for leaf cells). Changing how a cell would be netlisted as a module is harder - you'd have to overload the standard function to do this (which is theoretically possible as the netlisting system used in ADE is all SKILL++ based). However, it's not that straightforward to do that part if AMS is being used because you have to tell AMS to use a different formatter class.

    So I think this is going to be pretty hard. I think the best thing to do is to follow this up with customer support, as it's probably beyond what can really be covered on these forums... I can also do my bit to advise if you contact customer support (as you're in Europe and you can let whoever picks it up know that we've talked).

    Regards,

    Andrew.

Reply
  • Andrew Beckett

    Hi Jorg,

    Finally I have had a chance to read all this and reply (sorry it's taken me so long).

    If it had been a single potential and flow, you could have just defined a new discipline and then implemented your model that way. The fact that you want multiple solvants complicates matters.

    One possibility might be to use SystemVerilog and then User Defined Records which allow you to associate multiple real numbers with a port and transfer these between blocks. You'd have to use a signal flow approach rather than a conserved system (i.e. continuous in value, but discrete in time), but it would then allow you to transfer these complex signals between blocks without changing how the interfaces or wires are described. You could also VHDL models rather than SystemVerilog as these offer the same kind of construct.

    Changing the netlister to convert single wires to busses is quite tricky. There are two approaches to AMS netlisting; one of these is the "Cell-Based Netlister", and that's the document you've probably seen. The issue is that this is being deprecated in flavour of an OSS-based netlister (the latest version of this is known as UNL, or Unified Netlister, which addresses most of the shortcomings and implementation issues of the previous OSS-based netlister).

    The CBN approach required you to develop custom netlist procedures (if needed) for special things which were specific to AMS, and also have specific CDF entries for AMS. The OSS/UNL approach requires you to only customize for spectre (CDF and netlist procedures) and then the spectre syntax gets translated into Verilog-AMS syntax. This is for ease of maintenance, primarily.

    Typically all you can customize is how an individual instance is netlisted (and usually this is just for leaf cells). Changing how a cell would be netlisted as a module is harder - you'd have to overload the standard function to do this (which is theoretically possible as the netlisting system used in ADE is all SKILL++ based). However, it's not that straightforward to do that part if AMS is being used because you have to tell AMS to use a different formatter class.

    So I think this is going to be pretty hard. I think the best thing to do is to follow this up with customer support, as it's probably beyond what can really be covered on these forums... I can also do my bit to advise if you contact customer support (as you're in Europe and you can let whoever picks it up know that we've talked).

    Regards,

    Andrew.

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