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netlist formatter for spectre and AMS

Jorg

Hi Andrew,

I pray you'll find this and find the time to respond.

I want to write netlist formatters to be used with spectre and amsdesigner (different formatters for different simulators, of course).

What I found in the documentation is, how to integrate a new simulator, which seems to be meant for non-Cadence products.  In my case, it seems a overkill, since I do want to simulate with spectre, later maybe with amsdesigner.

The whole idea evolves around this problem: the electro-analogous systems, that I want to design, use signals which are single connections physically and bussed signals for simulation. For consistency, I want just one set of schematics and create appropriate netlists for simulation and physical verification from them.  Preferrably, the schematics would represent connections as single ports. Thus my idea to customize netlisting for spectre.

Could you please comment on where to best place the resolution of single vs bus for my purpose, and point me someplace how to start the netlist customization?

I also have looked at the netlist procedure property, that can be attached to a cell. This enables me, to manipulate how instances of this particular cell are printed into the netlist of a schematic. However, it leaves me with the problem, how to also manipulate the interface of this schematic netlist, i.e. the subckt/module definition.  Is there a similarily simple way to modify these as well?

 Thank you in advace for any hint and help.

Kind Regards,

Jörg

  •  

    Jorg said:

    The whole idea evolves around this problem: the electro-analogous systems, that I want to design,

    When you say "electro-analogous", do you mean like this?

    Jorg said:

    use signals which are single connections physically and bussed signals for simulation.

    Why? What does "physically" even mean in the context of this electro-analogous system?

    Jorg said:

    Could you please comment on where to best place the resolution of single vs bus for my purpose, and point me someplace how to start the netlist customization?

    I haven't delved deeply enough into the guts of the netlister to know how to do this, but I know it can be done.

    If you open a case with your AE, (s)he will have no choice but to help you. :)

     

  • Hi tweeks,

     

    tweeks said:

     

    The whole idea evolves around this problem: the electro-analogous systems, that I want to design,

    When you say "electro-analogous", do you mean like this?

    [/quote]

    Close, not exactly.  The system to be simulated is a fluidic system, so the potential/tension nature is pressure instead of voltage, and the flow nature is volumetric liquid flow instead of current.

     

    tweeks said:

    use signals which are single connections physically and bussed signals for simulation.

    Why? What does "physically" even mean in the context of this electro-analogous system?

    [/quote]

    The fluidic system is designed as schematic and layout, much like an IC.  Layout then gets exported to manufacturing data for a planar technology forming channels, valves, etc.  So on one hand my schematic will be used for layout verification. On the other hand the schematic is the starting point for simulations.  In the simulations, however, on top of the fluid itself, solvants in the fluid shall be regarded.  My idea was, to augment each conservative port that carries the liquid with an array of signal-flow ports, which will represent the solvants.  Out of one port and one wire drawn in the schematic, I want to create the augmented signals automatically in the netlisting. 

     

    tweeks said:

    Could you please comment on where to best place the resolution of single vs bus for my purpose, and point me someplace how to start the netlist customization?

    I haven't delved deeply enough into the guts of the netlister to know how to do this, but I know it can be done.

    [/quote] 

    Much the situation I find myself in.  

    Some digging into the AMS netlisting customization brought me to an old documet "Custom Netlist Procedures in AMS Designer" by Cadence of 2004.  I hope the procedures, variables, callbacks etc therein are still valid in dfII OA 6.1.6

    I'll return here and give a summary, when I'm done.

     

  • First, let me say that what you are doing is extremely interesting!

    The electrical concepts (voltage, current, resistance, capacitance) were first explained to me using the analogy of water flowing through pipes and into buckets, etc., and now here you are actually using electronics design software to design a fluidic system.  It's gone full-circle!

    I've also heard of people using commodity 3d graphics acceleraterator cards to make their circuit simulations go faster (becaues the vector/matrix calculations are done on special-purpose hardware), so there's another interesting, somewhat looser connection there between circuit systems and the way images are formed; i.e. the behavior of light.

    Anyway, sorry I can't be more helpful about customizing the netlister.  The documentation ought to be in there somewhere, but if it's too hard to figure out, I don't think it's out of the question to write your own netlister in SKILL from scratch: just walk down the schematic hierarchy, gather all the connectivity info you need, and then emit whatever text you want.  Figuring out how to obtain all the info you need from the schematics is not always simple either, due to the potential complications of the fancy wire/bus notation, but there are built-in functions you can use to parse them--never ever try to parse the Virtuoso Schematic wire expressions yourself!  I can help you if you decide to go this route, because I've written a schematic-scraper before--Andrew's probably written a few too.

       --tom

  • Hi Tom,

    This is going off-topic now, but draws my attention.

    tweeks said:

    The electrical concepts (voltage, current, resistance, capacitance) were first explained to me using the analogy of water flowing through pipes and into buckets, etc.,

    So was it to me, but at this time I had no clear concept of what pressure was, and did not grasp (nor was it explained to me) the clear distinction of flow and tension. So the "explanation" left me with one unknown concept being related to another unknown concept in an incomprehensible manner.

    In general I believe that teaching electricity to young people should explain the real concepts at an appropriate level of complexity, instead of analogies.  If you want to discuss this further, we'll ask the moderator to point us to an appropriate forum.


    tweeks said:

    I've also heard of people using commodity 3d graphics acceleraterator cards to make their circuit simulations go faster (becaues the vector/matrix calculations are done on special-purpose hardware), so there's another interesting, somewhat looser connection there between circuit systems and the way images are formed; i.e. the behavior of light.

    No.  It has nothing at all to do with image formation or any properties of light, but everything with the numerical mathematics inside the simulator.
    For an introduction, there is a very good book by Ken Kundert on how spectre works.  The title has a substring "spectre and spice", you'll find it.

    tweeks said:

    Anyway, sorry I can't be more helpful about customizing the netlister.  The documentation ought to be in there somewhere, but if it's too hard to figure out, I don't think it's out of the question to write your own netlister in SKILL from scratch: just walk down the schematic hierarchy, gather all the connectivity info you need, and then emit whatever text you want. 

    I don't think so.  The netlisters are highly configurable, in a overwhelming somewhat confusing diversity.  My question was about the right entry point into this for my purpose.
    If I would like to go the full way, there is OSS.   Also schematic hierarchy traversal is separated from netlist formatting. 
    And, I want this to be integrated in ADE, and use existing automations as far as possible.

    tweeks said:

    the potential complications of the fancy wire/bus notation, but

    not to mention net expressions, interpreted value strings for parameters, pcell call-backs, and the like.

    tweeks said:

    there are built-in functions

    Programmers tend to be lazy, I'm no exception.  If something is already there, use it.

    tweeks said:

    I can help you if you decide to go this route, because I've written a schematic-scraper before--Andrew's probably written a few too.

    Thank you. What is a schematic-scraper?


    Jorg

  • Hi Jorg,

    Finally I have had a chance to read all this and reply (sorry it's taken me so long).

    If it had been a single potential and flow, you could have just defined a new discipline and then implemented your model that way. The fact that you want multiple solvants complicates matters.

    One possibility might be to use SystemVerilog and then User Defined Records which allow you to associate multiple real numbers with a port and transfer these between blocks. You'd have to use a signal flow approach rather than a conserved system (i.e. continuous in value, but discrete in time), but it would then allow you to transfer these complex signals between blocks without changing how the interfaces or wires are described. You could also VHDL models rather than SystemVerilog as these offer the same kind of construct.

    Changing the netlister to convert single wires to busses is quite tricky. There are two approaches to AMS netlisting; one of these is the "Cell-Based Netlister", and that's the document you've probably seen. The issue is that this is being deprecated in flavour of an OSS-based netlister (the latest version of this is known as UNL, or Unified Netlister, which addresses most of the shortcomings and implementation issues of the previous OSS-based netlister).

    The CBN approach required you to develop custom netlist procedures (if needed) for special things which were specific to AMS, and also have specific CDF entries for AMS. The OSS/UNL approach requires you to only customize for spectre (CDF and netlist procedures) and then the spectre syntax gets translated into Verilog-AMS syntax. This is for ease of maintenance, primarily.

    Typically all you can customize is how an individual instance is netlisted (and usually this is just for leaf cells). Changing how a cell would be netlisted as a module is harder - you'd have to overload the standard function to do this (which is theoretically possible as the netlisting system used in ADE is all SKILL++ based). However, it's not that straightforward to do that part if AMS is being used because you have to tell AMS to use a different formatter class.

    So I think this is going to be pretty hard. I think the best thing to do is to follow this up with customer support, as it's probably beyond what can really be covered on these forums... I can also do my bit to advise if you contact customer support (as you're in Europe and you can let whoever picks it up know that we've talked).

    Regards,

    Andrew.

  • Hi Andrew,

    Thank you for your effort and the clearifying response.

    Andrew Beckett said:

    If it had been a single potential and flow, you could have just defined a new discipline and then implemented your model that way.

    So I've done for the liquid part of the story, and it works fine.

    Andrew Beckett said:

    One possibility might be to use SystemVerilog ....or VHDL....  and then User Defined Records which allow you to associate multiple real numbers with a port and transfer these between blocks. You'd have to use a signal flow approach rather than a conserved system...

    Yes.  This is clear to me, I have used this approach for discrete time modeling of analog blocks to be used in functional system verification.


    What I want here, is a mixture:  a conservative port augmented by several signal flow signals. One could of course also use a bus of conservative signals, and ignore the flow in the extra bits. But this would not really change the situation, since I still want to use the same schematic for simulation and physical verification.  One of the two netlists must be manipulated somehow, and I don't want the schematic in a way, such that my users could easily interfere with the simulation approach.


    Andrew Beckett said:

    The issue is that this (CBN) is being deprecated in flavour of an OSS-based netlister

    What a pity. I just found the AMS netlist procedures amsPrintPorts, amsPrintIOs, amsPrintWires which all could be overridden in CBN.  Isn't there something similar in the interface to the UNL netlisters?

    Andrew Beckett said:

    I think the best thing to do is to follow this up with customer support....

    I will email them. Thank you for offering some help with customer suppor, I wil probably need it.


    Meanwhile, I implement some examples with manually inserted extra ports, visible in the schematic, to develop the modeling and simulation approach.  Thus I'll know exactly what I want, when I lern a way to mangle the netlist.

    Kind Regards,

    Jörg

     

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