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netlist formatter for spectre and AMS

Jorg

Hi Andrew,

I pray you'll find this and find the time to respond.

I want to write netlist formatters to be used with spectre and amsdesigner (different formatters for different simulators, of course).

What I found in the documentation is, how to integrate a new simulator, which seems to be meant for non-Cadence products.  In my case, it seems a overkill, since I do want to simulate with spectre, later maybe with amsdesigner.

The whole idea evolves around this problem: the electro-analogous systems, that I want to design, use signals which are single connections physically and bussed signals for simulation. For consistency, I want just one set of schematics and create appropriate netlists for simulation and physical verification from them.  Preferrably, the schematics would represent connections as single ports. Thus my idea to customize netlisting for spectre.

Could you please comment on where to best place the resolution of single vs bus for my purpose, and point me someplace how to start the netlist customization?

I also have looked at the netlist procedure property, that can be attached to a cell. This enables me, to manipulate how instances of this particular cell are printed into the netlist of a schematic. However, it leaves me with the problem, how to also manipulate the interface of this schematic netlist, i.e. the subckt/module definition.  Is there a similarily simple way to modify these as well?

 Thank you in advace for any hint and help.

Kind Regards,

Jörg

Parents

  • Hi Andrew,

    Thank you for your effort and the clearifying response.

    Andrew Beckett said:

    If it had been a single potential and flow, you could have just defined a new discipline and then implemented your model that way.

    So I've done for the liquid part of the story, and it works fine.

    Andrew Beckett said:

    One possibility might be to use SystemVerilog ....or VHDL....  and then User Defined Records which allow you to associate multiple real numbers with a port and transfer these between blocks. You'd have to use a signal flow approach rather than a conserved system...

    Yes.  This is clear to me, I have used this approach for discrete time modeling of analog blocks to be used in functional system verification.


    What I want here, is a mixture:  a conservative port augmented by several signal flow signals. One could of course also use a bus of conservative signals, and ignore the flow in the extra bits. But this would not really change the situation, since I still want to use the same schematic for simulation and physical verification.  One of the two netlists must be manipulated somehow, and I don't want the schematic in a way, such that my users could easily interfere with the simulation approach.


    Andrew Beckett said:

    The issue is that this (CBN) is being deprecated in flavour of an OSS-based netlister

    What a pity. I just found the AMS netlist procedures amsPrintPorts, amsPrintIOs, amsPrintWires which all could be overridden in CBN.  Isn't there something similar in the interface to the UNL netlisters?

    Andrew Beckett said:

    I think the best thing to do is to follow this up with customer support....

    I will email them. Thank you for offering some help with customer suppor, I wil probably need it.


    Meanwhile, I implement some examples with manually inserted extra ports, visible in the schematic, to develop the modeling and simulation approach.  Thus I'll know exactly what I want, when I lern a way to mangle the netlist.

    Kind Regards,

    Jörg

     

Reply

  • Hi Andrew,

    Thank you for your effort and the clearifying response.

    Andrew Beckett said:

    If it had been a single potential and flow, you could have just defined a new discipline and then implemented your model that way.

    So I've done for the liquid part of the story, and it works fine.

    Andrew Beckett said:

    One possibility might be to use SystemVerilog ....or VHDL....  and then User Defined Records which allow you to associate multiple real numbers with a port and transfer these between blocks. You'd have to use a signal flow approach rather than a conserved system...

    Yes.  This is clear to me, I have used this approach for discrete time modeling of analog blocks to be used in functional system verification.


    What I want here, is a mixture:  a conservative port augmented by several signal flow signals. One could of course also use a bus of conservative signals, and ignore the flow in the extra bits. But this would not really change the situation, since I still want to use the same schematic for simulation and physical verification.  One of the two netlists must be manipulated somehow, and I don't want the schematic in a way, such that my users could easily interfere with the simulation approach.


    Andrew Beckett said:

    The issue is that this (CBN) is being deprecated in flavour of an OSS-based netlister

    What a pity. I just found the AMS netlist procedures amsPrintPorts, amsPrintIOs, amsPrintWires which all could be overridden in CBN.  Isn't there something similar in the interface to the UNL netlisters?

    Andrew Beckett said:

    I think the best thing to do is to follow this up with customer support....

    I will email them. Thank you for offering some help with customer suppor, I wil probably need it.


    Meanwhile, I implement some examples with manually inserted extra ports, visible in the schematic, to develop the modeling and simulation approach.  Thus I'll know exactly what I want, when I lern a way to mangle the netlist.

    Kind Regards,

    Jörg

     

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