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urgent - error with imported Verilog module

Hi all,

I imported a Verilog module in Virtuoso 6.1.6-64b and want to simulate it with AMS and OSS-based netlister. after the simulation I got a netlist error: strcat: argument #1 should be either a string or a symbol (type template = "S") - nill.

it's very strange because I used that verilog module in another test bench and it worked well.

thank you,

Katy

Andrew Beckett over 10 years ago

Hi Katy,

I think there is little chance of understanding this without seeing the data. Please contact customer support.

Regards,

Andrew.
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katyy over 10 years ago

Thanks, Andrew

finally I found that "S" - it's maybe about a string ,and indeed, it was the symbols and wire's names which included ' (to indicate not) and "x" . AMS simulator probably doesn't work well with those chars
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Andrew Beckett over 10 years ago

I think you're reading too much into the error message. All the error is telling you is that somewhere in the code some invalid data has been passed to the function strcat. It may well be that the code breaks as a consequence of some strange character, but if it does, that's a bug in our code - not that you've used an illegal character. If there's an illegal character, it should get mapped - not cause a SKILL error.

So you should really contact customer support to ensure this gets fixed.

Regards,

Andrew.
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