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urgent - error with imported Verilog module

katyy

Hi all,

I imported a Verilog module in Virtuoso 6.1.6-64b and want to simulate it with AMS and OSS-based netlister. after the simulation I got a netlist error: strcat: argument  #1 should be either a string or a symbol (type template = "S") - nill.

it's very strange because I used that verilog module in another test bench and it worked well.

thank you,

Katy

Parents

  • Thanks, Andrew

    finally I found that "S" - it's maybe about  a string ,and indeed, it was the symbols and wire's names which included  ' (to indicate not) and "x"  . AMS simulator probably doesn't work well with those chars

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  • Thanks, Andrew

    finally I found that "S" - it's maybe about  a string ,and indeed, it was the symbols and wire's names which included  ' (to indicate not) and "x"  . AMS simulator probably doesn't work well with those chars

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