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[SOLVED] Verilog-(AMS) PCell with variable bus width

Stepahn Walter

Hi,
i tried to build a parameterized Verilog module to work in a mixed Signal environment.
The goal is to simulate a full custom analog block in a top down design flow. Therefore, single parts of the design have to be swappable between verilog, verilog-ams and transistors (schematic).  An important point is, that the resolution of the analog block is not fixed. Therefore, i require for example a binary-to-thermo verilog decoder with a variable width, as well as a verilog-ams current mirror, also with variable width.


I was able to realize some parts as skill pcell schematics&symbols, where i just instantiate the verilog (-ams) symbol inside a new schematic. For the problems mentioned above, this is not possible. Therefore i tried to just build a skill pcell symbol for the verilog(-ams) cells. 


Simplified example of the decoder:

module DECODER #(parameter  BITS=3)(

input wire CLK,

input wire [(BITS-1):0] binary, //variable input vector

output reg [(2**BITS-1):0] thermo_p, //differential output

output reg [(2**BITS-1):0] thermo_n

);

wire [(2**BITS-2):0] select_high = {(2**BITS-1){1'b1}};  //generate a bus with all bits high

wire [(2**BITS-2):0] temp_select_high; //store the new output

assign temp_select_high = select_high >> binary[(MB-1):0];

always @(posedge CLK) begin

       thermo_p <= temp_select_high;

       thermo_n <= ~temp_select_high;

end

endmodule

First i tried to build a pcell symbol through the help of the skill function pcHICompileToSkill() and modifications to the so generated template. The problem is, that the neither the symbol change, nor the verilog seems to change.

My reserach point me to the following postings:

Cannot pass parameters from virtuoso sch. into Verilog module

and

How to pass a value to a pre-processor macro in a VerilogA view from CDF ?

Therefore, i tried the CDF editor example.


I add 2 component parameters to the Base layer.

Name BITS hnlVerilogCDFdefparamList
Prompt BITS hnlVerilogCDFdefparamList
Type string string
Default Value 3 BITS
Display Condition artParameterInToolDisplay('BITS) t
Parse as CEL YES YES
Parse as Number YES NO

There are no Callbacks defined.


As far as i understand the solution, the symbol should now change, and also BITS should be passed to the verilog module, but nothing happen, when i change the value of hnlVerilogCDFdefparamList or BITS. I only recieve the following warning, when i change them

*WARNING* (DB-270000): dbReplaceInstParamList: Datatype for input parameter 'BITS' does not match the definition

I really tried to solve the problem, but i have only found the two above posts, and they are no help for me.

I can't believe, that it is impossible to include a verilog(-ams) file as symbol into a schematic with a variable port width, so that i can have multiple instances with different values.

As far i know, it is no problem in a digital flow to specify just the parameterized modules, and include the analog block as a black box. But i want to use the digital part inside a analog schematic/environment, because nearly everything is analog.

Tank you very much for your help.

  • I have recognized, that i have forgotten to add the information about the software versions i use.
    ncsim(64) 14.10-s014
    virtuoso version 6.1.6-64b
    spectre version 13.1.1 64bit
    If there is still something missing, please say it, i will post the required information as soon as possible.

  • Ok, my search in the Cadence online Support brought me some more results. Perhaps the right?

    In "Virtuoso® AMS Designer Environment User Guide Product Version 6.1.6 June 2015" section 16 and 8 they explain how to handle PCells and CDF parameters through custom netlisting. Today i am not able to test it, but it sounds promising, because as explained, the problem is to pass the variables to the simulator.

    If somebody have already worked with customized netlists, and know, that it would not solve my problem, please say it. I have already wasted several working days on this topic.

  • Ok, we have found a solution that fit to most Verilog(-AMS) PCells, that require no custom netlister.

    There are two requirements for the Verilog(-AMS) cells.

    1. declare the variables as strings, and convert them inside the PCell Skill code. The netlister seems to can handle at least integers on this way.

    2. Do not use the default netlister.  You can change the netlister in ADE through

    Simulation->Netlist and Run Options ...

    and then in the new window click on  "AMS Unified Netlister with irun"

    This make it possible to use even Verilog(-AMS) PCells inside a schematic. The only problem still exist with the variable bus width.

    The schematic symbol of the Verilog(-AMS) PCell work for me, and also the connections are checked correct during save&check of the 
    schematic. The Problem is that the netlister does not pass the correct bus width to the cell. For example i rise the bus width from 8 to 16 
    for a binary to thermo decoder, and the netlister pass the right parameter to the cell and so on, but the he connect only 8 of the 16 output signals
    to the cell, and only the default 3 of the 4 for the input.

    EXAMPLE NETLIST:
    b_to_t_decoder #(.BITS(4), .number(12)) I2 (.thermo_n( net010[8:15] ), .thermo_p( net09[8:15] ), .binary( bin[2:0] ), .CLK( net3 )); 


    I have added the variable number to show, if the variables are passed through $display, and yes, it works! So if enybody have an idea 
    how i can fix the wrong port connection, please say it.


  • I have also solved the last problem with the wire connection.


    It seems, that the netlister can only map the size of the default port width. So if we specify 4 as default, we can mal 1-4 correct, but noch 5-n


    Therefore, we just have to specify the default parameters so, that the port have maximal width. Then everything runs as it should.

    I hope this will help other people to develop PCells for the siimulation in Mixed Signal environments with BIG analog and only little digital parts, as well as during high level simulations.

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