[SOLVED] Verilog-(AMS) PCell with variable bus width

Hi,
i tried to build a parameterized Verilog module to work in a mixed Signal environment.
The goal is to simulate a full custom analog block in a top down design flow. Therefore, single parts of the design have to be swappable between verilog, verilog-ams and transistors (schematic).  An important point is, that the resolution of the analog block is not fixed. Therefore, i require for example a binary-to-thermo verilog decoder with a variable width, as well as a verilog-ams current mirror, also with variable width.

I was able to realize some parts as skill pcell schematics&symbols, where i just instantiate the verilog (-ams) symbol inside a new schematic. For the problems mentioned above, this is not possible. Therefore i tried to just build a skill pcell symbol for the verilog(-ams) cells. 

Simplified example of the decoder:

module DECODER #(parameter  BITS=3)(

input wire CLK,

input wire [(BITS-1):0] binary, //variable input vector

output reg [(2**BITS-1):0] thermo_p, //differential output

output reg [(2**BITS-1):0] thermo_n

);

wire [(2**BITS-2):0] select_high = {(2**BITS-1){1'b1}};  //generate a bus with all bits high

wire [(2**BITS-2):0] temp_select_high; //store the new output

assign temp_select_high = select_high >> binary[(MB-1):0];

always @(posedge CLK) begin

       thermo_p <= temp_select_high;

       thermo_n <= ~temp_select_high;

end

endmodule

First i tried to build a pcell symbol through the help of the skill function pcHICompileToSkill() and modifications to the so generated template. The problem is, that the neither the symbol change, nor the verilog seems to change.

My reserach point me to the following postings:

Cannot pass parameters from virtuoso sch. into Verilog module

and

How to pass a value to a pre-processor macro in a VerilogA view from CDF ?

Therefore, i tried the CDF editor example.

I add 2 component parameters to the Base layer.

There are no Callbacks defined.

As far as i understand the solution, the symbol should now change, and also BITS should be passed to the verilog module, but nothing happen, when i change the value of hnlVerilogCDFdefparamList or BITS. I only recieve the following warning, when i change them

*WARNING* (DB-270000): dbReplaceInstParamList: Datatype for input parameter 'BITS' does not match the definition

I really tried to solve the problem, but i have only found the two above posts, and they are no help for me.

I can't believe, that it is impossible to include a verilog(-ams) file as symbol into a schematic with a variable port width, so that i can have multiple instances with different values.

As far i know, it is no problem in a digital flow to specify just the parameterized modules, and include the analog block as a black box. But i want to use the digital part inside a analog schematic/environment, because nearly everything is analog.

Tank you very much for your help.