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Measuring Layout Geometry

rafaelon

Hello friends from Cadence,

I have a layout with 1M transistors. I would like to obtain some information from it.

For example, the width and length of a specific interconnection.

I don't want to use the ruler. How could I do it using Skill language or other way?

Thanks,

Rafael

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  • rafaelon

    Andrew,

    Sorry for the delay.
    An example to clarify. The layout considered is composed by a main line named VDD with dozens of branches interconnecting parts of this circuit. We would like to obtain the dimension (width and length) from each VDD branch as also the main line. It would be interesting to obtain these dimensions in a txt table format with the name of each net and its dimensions. A Specific net mentioned in the last post could be the largest, for example. We are considering to implement this with SKILL code, but we believe that the virtuoso have this function implemented already. Could you help us to understand what is the best way?

    Regards,

    Rafael

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  • rafaelon

    Andrew,

    Sorry for the delay.
    An example to clarify. The layout considered is composed by a main line named VDD with dozens of branches interconnecting parts of this circuit. We would like to obtain the dimension (width and length) from each VDD branch as also the main line. It would be interesting to obtain these dimensions in a txt table format with the name of each net and its dimensions. A Specific net mentioned in the last post could be the largest, for example. We are considering to implement this with SKILL code, but we believe that the virtuoso have this function implemented already. Could you help us to understand what is the best way?

    Regards,

    Rafael

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