Measuring Layout Geometry

Rafael,

Can you please clarify precisely what you want to do here. How are you expecting to identify the "specific interconnection" here? What  do you even mean by "specific interconnection"?

Regards,

Andrew.

Andrew,

Sorry for the delay.
An example to clarify. The layout considered is composed by a main line named VDD with dozens of branches interconnecting parts of this circuit. We would like to obtain the dimension (width and length) from each VDD branch as also the main line. It would be interesting to obtain these dimensions in a txt table format with the name of each net and its dimensions. A Specific net mentioned in the last post could be the largest, for example. We are considering to implement this with SKILL code, but we believe that the virtuoso have this function implemented already. Could you help us to understand what is the best way?

Regards,

Rafael

Rafael,

This doesn't make any sense to me (and I don't think there's anything built-in to do this, because it seems a strange thing to want to do - I can't see what use this has). The table format you describe would be a bit odd, because all branches are on the VDD net - so wouldn't it just list VDD for all segments? Also, what do you mean by a "branch" - you could have a main VDD trunk (with bends in it) with branches coming off that trunk (which might have bends in them) and then twigs coming off each of those branches. What do you consider to be a branch? Any time the track changes direction? It's rather hard to determine what you really want here - maybe a picture would help? Why do you need this information anyway?

Not that I can necessarily write this for you - but I might be able to steer you in the right direction to write it yourself, assuming that there is some way of distinguishing what you mean by a branch.

Regards,

Andrew.

Andrew,

First, we appreciate your time dedicated in this question.

We inserted a Figure to exemplify our intentions.

We are evaluating the reliability from part of the VDD line.

We are assuming that VDD_1_8, for example, is the bottleneck.

So, it is important to construct that table to evaluate our circuit.

Thanks,

Rafael

Rafael,

OK, it looks as if you're trying to assess the potential electromigration failures using a rather simplistic approach. It's not much more than dumping out the dimensions of all the shapes you find on a particular net. This gives no heed as to whether there would actually be significant (or even any) current flow through a particular track; you might have a diminishing number of current sources or sinks further down the trunk and so it's OK to have smaller track widths there, but near the point at which the supply is connected, you might have much more current flowing through a particular track. Dealing with parallel tracks (both to the side or above/below) would also alter the assessment of whether you have a problem or not.

Cadence already has tools to do this type of electromigration analysis (e.g. Voltus-Fi for signoff and Virtuoso Electrically Aware Design (EAD) for in-design, plus the older Virtuoso Power System (VPS)) which all use simulation to determine the current flows through the devices and can better solve the actual current flows through the tracks and be much more realistic than simply measuring the width and length of the tracks. These will deal with the fact that you have parallel paths and give you a much more accurate answer.

Would it not make sense to use these tools instead?

Kind Regards,

Andrew.

Unknown said:

We don't know very well how these tools work (Voltus-Fi, EAD and VPS), but we think that , for electromigration analysis , they calculate the current density from each line and compare with the maximum current density supported (obtained in the technology process datasheet). We are correct?

Yes, that's correct. The EM rules often are supplied in an "ICT" file or QRC tech file, or even an emData file (various formats), and that's what these tools use.

I don't know of anything we have that looks at stressmigration. I was not aware of it being a significant issue in most technologies (that may just be my lack of knowledge, but I don't think I've ever had anyone ask me about it).

Regards,

Andrew.