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Measuring Layout Geometry

rafaelon

Hello friends from Cadence,

I have a layout with 1M transistors. I would like to obtain some information from it.

For example, the width and length of a specific interconnection.

I don't want to use the ruler. How could I do it using Skill language or other way?

Thanks,

Rafael

Parents
  • Andrew Beckett

    Rafael,

    OK, it looks as if you're trying to assess the potential electromigration failures using a rather simplistic approach. It's not much more than dumping out the dimensions of all the shapes you find on a particular net. This gives no heed as to whether there would actually be significant (or even any) current flow through a particular track; you might have a diminishing number of current sources or sinks further down the trunk and so it's OK to have smaller track widths there, but near the point at which the supply is connected, you might have much more current flowing through a particular track. Dealing with parallel tracks (both to the side or above/below) would also alter the assessment of whether you have a problem or not.

    Cadence already has tools to do this type of electromigration analysis (e.g. Voltus-Fi for signoff and Virtuoso Electrically Aware Design (EAD) for in-design, plus the older Virtuoso Power System (VPS)) which all use simulation to determine the current flows through the devices and can better solve the actual current flows through the tracks and be much more realistic than simply measuring the width and length of the tracks. These will deal with the fact that you have parallel paths and give you a much more accurate answer.

    Would it not make sense to use these tools instead?

    Kind Regards,

    Andrew.

Reply
  • Andrew Beckett

    Rafael,

    OK, it looks as if you're trying to assess the potential electromigration failures using a rather simplistic approach. It's not much more than dumping out the dimensions of all the shapes you find on a particular net. This gives no heed as to whether there would actually be significant (or even any) current flow through a particular track; you might have a diminishing number of current sources or sinks further down the trunk and so it's OK to have smaller track widths there, but near the point at which the supply is connected, you might have much more current flowing through a particular track. Dealing with parallel tracks (both to the side or above/below) would also alter the assessment of whether you have a problem or not.

    Cadence already has tools to do this type of electromigration analysis (e.g. Voltus-Fi for signoff and Virtuoso Electrically Aware Design (EAD) for in-design, plus the older Virtuoso Power System (VPS)) which all use simulation to determine the current flows through the devices and can better solve the actual current flows through the tracks and be much more realistic than simply measuring the width and length of the tracks. These will deal with the fact that you have parallel paths and give you a much more accurate answer.

    Would it not make sense to use these tools instead?

    Kind Regards,

    Andrew.

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