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  3. Generating verilog netlist from schematic

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Generating verilog netlist from schematic

JagdishP
JagdishP over 8 years ago

Hi,

I am trying to generate verilog netlist from the schematic view of the circuit I am working on.

For doing so I follow following steps---->

1. open schematic.

2. under Launch tab, click on Plugins-->Simulations-->NCVerilog.

3. after this I get a window called "Virtuoso Verilog Environment for NC-Verilog Integration"

4. Then I choose the appropriate Run Directory and Initialise the design.

5. After this I choose to generate netlist option.

Now I am facing an error while generating the netlist. the CIW window says " *Error* eval: undefined function - hnlSetOutputVars ".

What is this error and how can I solve this error. Can anybody help?

Regards,

Jagdish

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  • Andrew Beckett
    Andrew Beckett over 8 years ago

    Hi Jagdish,

    That's odd. I've not found reports of this - it suggests that the netlister is not being loaded properly. I couldn't quite find any direct reports for this related to the NC-Verilog integration (a few other cases of using "si" standalone for certain other netlisters, but not for NC Verilog).

    Which IC subversion are you using (Help->About will tell you this)?

    Regards,

    Andrew.

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  • Andrew Beckett
    Andrew Beckett over 8 years ago

    Hi Jagdish,

    That's odd. I've not found reports of this - it suggests that the netlister is not being loaded properly. I couldn't quite find any direct reports for this related to the NC-Verilog integration (a few other cases of using "si" standalone for certain other netlisters, but not for NC Verilog).

    Which IC subversion are you using (Help->About will tell you this)?

    Regards,

    Andrew.

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