Stats

  • Locked Locked
  • Replies 8
  • Subscribers 143
  • Views 28316
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Generating verilog netlist from schematic

JagdishP

Hi,

I am trying to generate verilog netlist from the schematic view of the circuit I am working on.

For doing so I follow following steps---->

1. open schematic.

2. under Launch tab, click on Plugins-->Simulations-->NCVerilog.

3. after this I get a window called "Virtuoso Verilog Environment for NC-Verilog Integration"

4. Then I choose the appropriate Run Directory and Initialise the design.

5. After this I choose to generate netlist option.

Now I am facing an error while generating the netlist. the CIW window says " *Error* eval: undefined function - hnlSetOutputVars ".

What is this error and how can I solve this error. Can anybody help?

Regards,

Jagdish

  • Hi Jagdish,

    That's odd. I've not found reports of this - it suggests that the netlister is not being loaded properly. I couldn't quite find any direct reports for this related to the NC-Verilog integration (a few other cases of using "si" standalone for certain other netlisters, but not for NC Verilog).

    Which IC subversion are you using (Help->About will tell you this)?

    Regards,

    Andrew.

  • Hi Andrew, I am using version IC6.1.6.500.14

  • I've just tried in that version and it works fine for me. I wonder if you have a .simrc file somewhere which is causing trouble (check in your working dir or home dir to start off with).

    If not, I think contacting customer support is the best option.

    Regards,

    Andrew.

  • Hi Andrew,
    I re-invoked virtuoso, and to my surprise its generating netlist now... :) :)
    As of now, I got what I wanted to do, but this re-invoking thing is not the solution to the problem.

    Regrads,
    Jagdish

  • Jagdish,

    You might be seeing a symptom of what is described in this article. If you create a netlist in ADE and then use the NC-Verilog integration in the same session (in IC616) then it breaks (the error mentioned there is not exactly the same, but it's similar). That's fixed in IC617.

    Regards,

    Andrew.

  • I guess it makes sense Andrew, because I tried creating netlist from ADE L initially, later on I realised that verilog netlisting cant be done via ADE and so switched to NCVerilog in the same session.

    Thanks a lot Andrew.

    Regards,
    Jagdish
  • in reply to Andrew Beckett

    Hi Andrew,

    Can you tell me how to change the port ordering of buses in the verilog file which is generated by tool in virtuoso?

    Currently while generating, i see the buses with low to high { [0:4] for eg} port map. I need it to be generated from high_to_low ports{ [4:0] for eg}. Which option in the NC-Sim allows this to be changed?

    regards,

    Jagdish

  • in reply to JagdishP

    Can you clarify what you mean here? Perhaps give an example of what the schematic looks like, what the portion of the netlist looks like, and what you want?

    Generally posting on the end of an old thread isn't a good idea (even if it was yours) because it means it's less clear what topic the question was on and it makes it harder for somebody to reuse the info.

    Regards,

    Andrew.

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.