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Generating verilog netlist from schematic

JagdishP

Hi,

I am trying to generate verilog netlist from the schematic view of the circuit I am working on.

For doing so I follow following steps---->

1. open schematic.

2. under Launch tab, click on Plugins-->Simulations-->NCVerilog.

3. after this I get a window called "Virtuoso Verilog Environment for NC-Verilog Integration"

4. Then I choose the appropriate Run Directory and Initialise the design.

5. After this I choose to generate netlist option.

Now I am facing an error while generating the netlist. the CIW window says " *Error* eval: undefined function - hnlSetOutputVars ".

What is this error and how can I solve this error. Can anybody help?

Regards,

Jagdish

Parents
  • I guess it makes sense Andrew, because I tried creating netlist from ADE L initially, later on I realised that verilog netlisting cant be done via ADE and so switched to NCVerilog in the same session.

    Thanks a lot Andrew.

    Regards,
    Jagdish
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  • I guess it makes sense Andrew, because I tried creating netlist from ADE L initially, later on I realised that verilog netlisting cant be done via ADE and so switched to NCVerilog in the same session.

    Thanks a lot Andrew.

    Regards,
    Jagdish
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