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calculator numconv function

abdurrahman0234
abdurrahman0234 over 4 years ago

When ı plot to calculator, I get error as below. I want to convert binary signal to decimal.Please can help me. 

ERROR (VIVA-3002):expression evaluation failed: val is not legal.
ERROR (VIVA-3002):expression evaluation failed: numConv(VT("/out<0:2>") "dec" t)

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  • abdurrahman0234
    abdurrahman0234 over 4 years ago

    sorry, when ı send my plot to calculator

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  • Andrew Beckett
    Andrew Beckett over 4 years ago in reply to abdurrahman0234

    I think you should use the analog to digital functions that were referenced in the other thread you posted in after this. The numConv is really for single valued text numbers and will convert them into a different number base. I don't think it's the right solution here.

    Andrew

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  • abdurrahman0234
    abdurrahman0234 over 4 years ago in reply to abdurrahman0234

    while converted digital to analog, high and low voltages range is; -4*840m for low and 3*840m for the decimals between  -4 and 3?

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  • abdurrahman0234
    abdurrahman0234 over 4 years ago in reply to abdurrahman0234

    (vhi+vlo)/2 this formula is constant?

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  • Andrew Beckett
    Andrew Beckett over 4 years ago in reply to abdurrahman0234

    That's rather up to you. It depends on what you want the range of the final "analog" representation of the bus to be. It could be -4 and 3. I don't really see why you'd need to multiply it by 840mV.

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  • abdurrahman0234
    abdurrahman0234 over 4 years ago in reply to Andrew Beckett

    because first high bit voltage level 840m

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  • Andrew Beckett
    Andrew Beckett over 4 years ago in reply to abdurrahman0234

    I assume you're referring to the X: (vhi+vlo)/2. That is indicating what voltage would be used if there are any "unknowns" in the digital waveform. There won't be if you use the "Center" mode in the analog to digital (you'll only get X if you have used the High/Low setting on analog to Digital, and the signal stays between the low and the high for longer than a certain time).

    Andrew

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  • Andrew Beckett
    Andrew Beckett over 4 years ago in reply to abdurrahman0234
    abdurrahman0234 said:
    because first high bit voltage level 840m

    As I said, it's entirely up to you. I can't really see why you would need to scale it, but presumably you know what you're trying to do with the result!

    Anyway, hopefully all is clear now.

    Andrew 

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  • abdurrahman0234
    abdurrahman0234 over 4 years ago in reply to Andrew Beckett

    I wanted to say, for example, -4 deciöal number, voltage level 840*-4 or x*-4. x depends on the before voltage level

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  • abdurrahman0234
    abdurrahman0234 over 4 years ago in reply to Andrew Beckett

    thanks very much Sir.  I get below error while simulate psd.How can I solve this?

    The signal x-axis vector values are not uniformely distributed. Data was interpolalated, which would create numerical noise and differences. To remove these errors, use uniform raw data points.

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  • Andrew Beckett
    Andrew Beckett over 4 years ago in reply to abdurrahman0234

    It's not an error, it's a warning. However, given that the signal you're trying to do the PSD/FFT on is highly discretised (it's only a 3-bit bus after all), it probably makes sense to use the "Zero T" transition choice on the Digital to Analog form rather than "Piecewise Linear":

    You'll see the difference in the transitions as follows in the results (I've shown the output of the bus converted both ways):

    (the red is the piecewise linear, the orange is Zero-T).

    You will probably still get the warnings, but at least you know that there would be no interpolation. If the red curve had been used, then the sample points would have been between the discrete bus transitions and that's probably not what you wanted (I don't really know what you're trying to do with the PSD, but I doubt you'd want interpolated values to be used in the PSD/FFT).

    Of course, you want to ensure that your sampling in the PSD is related to the clock rate of the data, but I'm sure you realise that.

    Regards,

    Andrew

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  • abdurrahman0234
    abdurrahman0234 over 4 years ago in reply to Andrew Beckett

    but, I get these warning all of time.When I use zero-t  or analog plot, too, ı get these warning. 

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  • abdurrahman0234
    abdurrahman0234 over 4 years ago in reply to Andrew Beckett

    but, I get these warning all of time.When I use zero-t  or analog plot, too, ı get these warning. 

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  • abdurrahman0234
    abdurrahman0234 over 4 years ago in reply to abdurrahman0234

    Ok, Sır, I will change clk rate and I will test again. Thank u

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  • Andrew Beckett
    Andrew Beckett over 4 years ago in reply to abdurrahman0234
    abdurrahman0234 said:
    but, I get these warning all of time.When I use zero-t  or analog plot, too, ı get these warning

    Yes, as I said, this will not remove the warning, but it will stop it interpolating which is what the message is primarily alerting you to. In general, if the input waveform does not contain regularly spaced time points (and those time points coincide with the sample points for the PSD/FFT) then there will need to be interpolation to re-sample at the points needed for the PSD/FFT. This warning is a fairly generic warning that gets triggered when it's clear there is sampling/interpolation needed (there are conditional parts of the warning depending on what has to happen). With an analog waveform you can do things like use strobeperiod in the transient analysis to only have an output at a regular timestep which improves accuracy and removes the need to interpolate. In your case however, this wouldn't help - the irregular x points are coming from the fact that the bus only has a time point when the bus value changes, and hence the bus converted to analog is similar.

    As I said, if you've used Zero T, you can ignore the warning - you are sampling at discrete values and so it doesn't really matter that the time steps are not regular.

    Andrew

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  • Andrew Beckett
    Andrew Beckett over 4 years ago in reply to abdurrahman0234
    abdurrahman0234 said:
    Ok, Sır, I will change clk rate and I will test again. Thank u

    I didn't say you needed to change the clock rate. I was merely saying that you need to ensure in the psd function or dft that the number of samples and the time interval you are running over results in a sample interval that corresponds to the same data rate as your bus is changing at. That data rate is presumably related to your clock frequency - it is unlikely to make sense to sample at some interval completely unrelated to the clock period. That's all I was saying.

    Andrew

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