Re: prevent string choices of verilogA from splitting into two lines

Hi,

I created a verilogA block to generate different static output depending on a parameter call Mode that can have two values, "power down" and "calibration". This verilogA is instantiated on a schematic view and the chosen values is determined by a pull down menu by modifying the CDF of this block where Mode is set as a cyclic button and choices having the following entry: power down,calibration

The verilogA code is as follow:

// VerilogA for sandbox, simCell_DAC, veriloga

`include "constants.vams"
`include "disciplines.vams"

module simCell_DAC (VDD, VSS, DAC_D);

output [1:0] DAC_D;
inout VDD, VSS;

electrical [1:0] DAC_D;
electrical VDD, VSS;

integer VAL_DAC_D=0;

parameter string Mode = "power down";

genvar i;

analog begin

case (Mode)
"power down" : VAL_DAC_D = 1;
"calibration" : VAL_DAC_D = 3;
default: VAL_DAC_D = 2;
endcase

for (i=1; i>=0; i=i-1) begin
V(DAC_D[i],VSS) <+ (VAL_DAC_D>>i)&1 ? V(VDD) : V(VSS);
end

end

endmodule

On the occasion where the netlister splits the "power down" into two lines like below

  I0 (VDD_TOP VSS_TOP DOUT\<1>\ DOUT\<0\>) simCell_DAC Mode="power \

down"

the default option within the case-statement will be called instead of the "power down". Is there a way to either prevent the netlister from splitting the "power down" string into two lines or verilogA case statement to accept breakage?