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Is there a way to generate netlist automatically with recurrence in Virtuoso(from schematic)?

Hi,

We are working in a project with multiple designer and I am maintaining the top level of the design. I am looking if there is a way to generate a netlist recurringly(like every night) in Virtuoso environment such that the design is always netlistable. I know couple ways to generate the netlist manually but I want to do this automatically in terminal with some script. There will be later post-processing log file if it passes or fails(and further actions like sending an email).

In case it is needed, these are spectre and versions

spectre -W => sub-version 20.1.0.231.isr6

ICADVM20.1-64b.NY_201ISR19

Thanks

yayla

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Andrew Beckett over 3 years ago

Presumably you could use this: Generating Verilog Netlist from UNIX command line for Schematic Design and License requirement

Whether the design is netlistable will depend on whether it has been checked before being saved.

Andrew
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Andrew Beckett over 3 years ago

Presumably you could use this: Generating Verilog Netlist from UNIX command line for Schematic Design and License requirement

Whether the design is netlistable will depend on whether it has been checked before being saved.

Andrew
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