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Include Verilog-A module SpiceIn

DanGua

Hello,

I have a ring oscillator to which the frequency is unknow, and there is a wide gap between the slowest and fastest corners. So the Stop Time cannot be fixed or it would take a lot of time to cover the high frequencies. Very similar to this case: https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/48392/transient-stop-time-for-specified-number-of-clocks 

I have followed the answers provided in the link and built a Verilog-A module to stop the simulation after 10 cycles. This works pretty good while using Virtuoso GUI.

However, I'm working with some scripts to automate the process, where the SPICE netlist is imported by "spiceIn" command and simulations are run through oceanScripts. The problem is that I cannot include the Verilog-A module into the netlist and import it by "spiceIn", because the tool cannot find the module.

The netlist content looks like this:

simulator lang=spectre

ahdl_include "counter.va"

X0 (in1, in2) counter

I will get the following error:

ERROR (SPICEIN-24): Spice In did not find the symbol view of the master cell 'counter' of the instance 'X0' in the subcircuit 'top'. Specify the reference library that has the symbol.

So far the only workaround I've found is to import the netlist without the VerilogA module, open Virtuoso GUI and create a VerilogA cellview and symbol and then instantiate it in the schematic view of the original circuit. Later I can run the simulations with the oceanScript. But this is time consuming and I need a way to fully automate the process.

Thanks,

Daniel

  • Daniel,

    First of all, it sounds as if you don't really need to import the netlist using spicein (unless you have a very strong reason to do so). You can run OCEAN where the design() is a netlist instead, so maybe that's the best solution?

    If you want to do this, you need to ensure that the netlist is called "netlist" and there are empty files called netlistHeader/netlistFooter in the same directory - ideally you are replicating the same kind of directory structure that ADE uses.

    If you really need to SPICEIN something that has an instance of a Verilog-A view, you will indeed have to create a symbol for that and the view itself. Unfortunately the cdsTextTo5x command doesn't handle importing Verilog-A (this is the second time this has come up in the last couple of days, strangely, having not had this come up before). You could do it with the code in 11239088 (with an appropriate view type), then vmsUpdateCellViews() to create the netlist.oa and then something like 

    schViewToView("solns" "va_crea" "solns" "va_crea" "veriloga" "symbol" "ahdlToPinList" "schPinListToSymbolGen")

    to create the symbol. 

    Andrew

  • in reply to Andrew Beckett

    Hi Andrew,

    Thank you for your reply. There is really not a reason I need to use spiceIn, I'm new to this and I started using Virtuoso GUI and I'm progressively moving to scripts. So I'm taking your first approach and dropping spiceIn.

    I have an OceanXL script exported from ADE explorer, a directory named netlist, which includes the netlist called "netlist", the netlistHeader and netlistFooter files.

    I've changed the OCEAN to point to the netlist: design( "<path>/netlist/netlist" )

    The netlist instantiates some subckts defined in a CDL. When running the simulation, I will encounter errors similar to these:

    Error found by spectre in `AND2X005', during circuit read-in.
    ERROR (SFE-400): "*****.cdl" 866: Cannot run the simulation because the master name specified for instance 'MN6' is invalid. Specify a valid master name and rerun the simulation.
    ERROR (SFE-400): "*****.cdl" 867: Cannot run the simulation because the master name specified for instance 'MN7' is invalid. Specify a valid master name and rerun the simulation.

    Any idea why the include of the CDL in the netlist would fail with spectre, while it didn't fail with spiceIn?

    I've tried already adding "simulator lang=spice" before including the CDL file.

    Thanks,

    Daniel

  • in reply to DanGua

    Hi Daniel,

    CDL is not SPICE. It's SPICE-like in syntax, but typically each transistor has a subtype used for recognition in LVS and that's not necessarily the same as the model name used for simulation. CDL is intended for physical verification and not for simulation. There are times where it might be OK for both if written appropriately, but it seems likely in this case that the models don't match the names in the CDL file.

    With SPICEIN that goes away because you map the particular CDL subtype to a PDK device which then netlists for Spectre with the appropriate spectre model name.

    I'm guessing a bit here as I can't see your data, but this seems a likely explanation to me.

    Andrew 

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