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Auto Via with overlap prevention between consecutive VIAs

KSSB
KSSB over 2 years ago

Hi, 

Using the ICADV20.1 ISR 27. and 180nm node. The question is related to the layout XL Auto Via command. 

When I use Auto Via command among the Metal1, Metal2 and Metal3, I see that the VIA1 and VIA2 are overlapped. 

Is there any option or a way to force auto Via to avoid the stacking vias/overlap. Here is the image

Appreciate your help.

Thanks

Baig

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  • KSSB
    KSSB over 2 years ago

    I tried to edit the constraint group to prevent stack. But it is still not working. As I didn't get any response, it looks like the only option left is to use abe layers to get overlap and move/delete the stacked visa.

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  • Andrew Beckett
    Andrew Beckett over 2 years ago in reply to KSSB

    I wouldn't normally expect there to be any issue with stacking vias in 180nm technology - usually planarized processes don't have a problem - it was only in older technologies where there was no planarization. As such, there seems to be limited support for preventing stacked vias - the stackable constraint (also called viaStackAllowed) is not currently supported by the via engine, and there is some limited support for an alternative (viaStackLimit); this seems to work with changing layers when creating wires, but not by the auto-via. I was going to speak to the R&D team responsible but it's a public holiday for much of Europe today; I would suggest that if this is important you contact customer support as this would allow a change request to be filed on your behalf.

    KSSB said:
    As I didn't get any response

    You posted on a Friday on the community forums (which is not the formal support site) and then noted about this being an issue still on the following Monday. Forum questions are answered by people in their spare time (including those of us at Cadence) - if you have more urgency, you should use customer support as that's what it's for...

    Andrew

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