How to find gate resistance?

Dear mars32,

mars32 said:

Hello, I am trying to find the gate resistance of my transistor in Cadence Virtuoso. I am using slvtnfet_mmw_5t in the 22nm kit. I have noticed that in the result browser, there are values such as rgres, rgres1, rgg_c1c2, rgg_c2c3, rgg_c3, rgg_m1m2, rgg_m2c1, however, there is no explanation as to the meaning of any of them

To my knowledge, the gate resistance is not a parameter included in the core BSIM-IMG model. The main reason is that the real part of the gate input impedance is highly dependent on the layout and not solely the geometric parameters of the device. The physical layout of the trace to the defined physical gate and the number of vias in the trace and connecting to the physical gate itself are highly variable. Some schematic models use a macromodel that contains the core BSIM_IMG model surrounded by networks to better model the estimate layout parameters (see Figure 1 from reference [1]).

I am not sure if you are running a simulation using a netlist composed from the schematic view or a layout based extracted view of your transistor. If the latter, the traces to the physical gate are based on the layout and any resistance in the trace (including via resistances) may be fractured to include parasitic layout capacitors. As a result, it is likely there is not one resistor that models the gate resistance in the netlist. Further, the real impedance of the gate is frequency dependent and hence knowing just a single gate resistor in the netlist is likely not going to provide an accurate model of the net "gate resistance".  All of these facts are totally consistent with your observation:

mars32 said:

I tried doing a test circuit with a simple s-parameter simulation with 1 transistor and a port at the gate of my transistor and looked at the real value of z at that point, and it does not correspond with any of the mentioned rgres, rgg, etc.. I cannot run the s-paramter simulation in my actual circuit where I need it.

I am not sure what your need for the overall gate real impedance is, but it may also be determined by a transient or AC analysis by examining the real input impedance of the node in your circuit at which you define the transistor gate. Perhaps these analyses are more compatible with your simulation needs.

I hope I correctly understood your question and apologize if I did not!

Shawn

Figure 1

[1]C. Hu, S. Khandelwal, Y. S. Chauhan, T. Mckay, J. Watts, J. P. Duarte, P. Kushwaha, & H. Agarwal (Eds.), Industry standard FDSOI compact model BSIM-IMG for IC design (pp. 65-87). (Woodhead Publishing Series in Electronic and Optical Materials). Elsevier. doi.org/.../B978-0-08-102401-0.00004-2

Dear mars32,

My post was flagged as spam. Hopefully it will be released. The figure I intended  to attach was also not included as the reply was posted when I logged in (I did not post the reply...this is a continual issue with the Forum software). Nevertheless, Figure 1 is attached.

Shawn

Figure 1

Figure 8.12b from reference [1]

Hello Shawn, 

Thank you for the insight! Would this also be true in regard to the back gate resistance as well?

Dear mars32,

I am happy to read you thought it was of some help!

mars32 said:

Would this also be true in regard to the back gate resistance as well?

If I understand your term  "back gate resistance" as referring to the impedances between the bulk connection of the device and its substrate, then I agree it is not included in the model. Referring to Figure 1 included in my prior post, note that the node labeled "B", which represents the bulk node, has a number of impedances ( 5 R's and 5 C's) between the node "B" and the actual bulk node of the BSIM_IMG model.

I hope I understood your question correctly!

Shawn