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  3. How to find gate resistance?

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How to find gate resistance?

mars32
mars32 over 2 years ago

Hello, I am trying to find the gate resistance of my transistor in Cadence Virtuoso. I am using slvtnfet_mmw_5t in the 22nm kit. I have noticed that in the result browser, there are values such as rgres, rgres1, rgg_c1c2, rgg_c2c3, rgg_c3, rgg_m1m2, rgg_m2c1, however, there is no explanation as to the meaning of any of them, therefore I don't know if they are what I want. 

I tried doing a test circuit with a simple s-parameter simulation with 1 transistor and a port at the gate of my transistor and looked at the real value of z at that point, and it does not correspond with any of the mentioned rgres, rgg, etc.. I cannot run the s-paramter simulation in my actual circuit where I need it.

I have also tried looking through the BSIM-IMG documentation but have not figured it out from there. 

Does anyone know if one of the rgres, rgg values is correct or if any documentation explains it anywhere? Or does anyone have any idea on how else I could find the gate resistance? 

Thank you.

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  • ShawnLogan
    ShawnLogan over 2 years ago

    Dear mars32,

    My post was flagged as spam. Hopefully it will be released. The figure I intended  to attach was also not included as the reply was posted when I logged in (I did not post the reply...this is a continual issue with the Forum software). Nevertheless, Figure 1 is attached.

    Shawn

    Figure 1

    Figure 8.12b from reference [1]

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  • mars32
    mars32 over 2 years ago in reply to ShawnLogan

    Hello Shawn, 

    Thank you for the insight! Would this also be true in regard to the back gate resistance as well?

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  • mars32
    mars32 over 2 years ago in reply to ShawnLogan

    Hello Shawn, 

    Thank you for the insight! Would this also be true in regard to the back gate resistance as well?

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  • ShawnLogan
    ShawnLogan over 2 years ago in reply to mars32

    Dear mars32,

    I am happy to read you thought it was of some help!

    mars32 said:
    Would this also be true in regard to the back gate resistance as well?

    If I understand your term  "back gate resistance" as referring to the impedances between the bulk connection of the device and its substrate, then I agree it is not included in the model. Referring to Figure 1 included in my prior post, note that the node labeled "B", which represents the bulk node, has a number of impedances ( 5 R's and 5 C's) between the node "B" and the actual bulk node of the BSIM_IMG model.

    I hope I understood your question correctly!

    Shawn

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