Is there any guide as to what the different result in Cadence Virtuoso mean? Example, cbg, cbb in the dcOpinfo result browser

Dear mars32,

mars32 said:

There is cbg, cgb, etc.. I assumed cbg might be the capacitance of the back gate while cgb is the capacitance of the gate to bulk but I'm not sure and I'm not sure where I could find this information.

I think a good resource is the Spectre Circuit Simulator Components and Device Models Reference. You may find this on the Cadence on-line Support site or it used to be included in your installation directory hierarchy at:

 <SPECTREinstDir>/doc/spectremod/spectremod.pdf

and hopefully still is!

There is a section entitled "MOS Capacitance Model" that is likely relevant.

Shawn

MOS Capacitance Model

Shawn

Dear mars32,

mars32 said:

There is cbg, cgb, etc.. I assumed cbg might be the capacitance of the back gate while cgb is the capacitance of the gate to bulk but I'm not sure and I'm not sure where I could find this information.

I think a good resource is the Spectre Circuit Simulator Components and Device Models Reference. You may find this on the Cadence on-line Support site or it used to be included in your installation directory hierarchy at:

 <SPECTREinstDir>/doc/spectremod/spectremod.pdf

and hopefully still is!

There is a section entitled "MOS Capacitance Model" that is likely relevant.

Shawn

MOS Capacitance Model

Shawn

Hi Shawn,

Thank you for the help! I found some of the operating point parameters under BSIM-4, although I couldn't find them for BSIM-IMG but there was enough overlap. 

Do you know where I could find the definitions for something more specific to the 22nm kit? For example, in the results browser, under dcOpInfo, for the mosfet slvtnfet_mmw_5t, there are the normal dc operating point parameters, but there are 2 other folders, one named x_sub, and one named slvtnfet_mmw_5t, each with more operating point parameters, and these are nowhere to be found in the document, as I assume it's specific to the 22nm kit since it has an extra back gate.

Dear mars,

mars32 said:

I found some of the operating point parameters under BSIM-4, although I couldn't find them for BSIM-IMG but there was enough overlap. 

Well, I am happy to read it helped you inch along the way anyway - but not quite enough to satisfy your need - sorry!

mars32 said:

Do you know where I could find the definitions for something more specific to the 22nm kit? For example, in the results browser, under dcOpInfo, for the mosfet slvtnfet_mmw_5t, there are the normal dc operating point parameters, but there are 2 other folders, one named x_sub, and one named slvtnfet_mmw_5t, each with more operating point parameters, and these are nowhere to be found in the document,

I do not have access to the 22 nm kit as am not working in that technology. However, from my experiences with other PDK, I have a thought as to what the two folders may represent. Let me pass it by you for your consideration. I think I included much of this information in a prior Forum post you asked a couple months back at URL:

https://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/57806/how-to-find-gate-resistance

Often, when a PDK is assembled by either the relevant foundry or a company using the technology, there are two models created from the base BSIM model. One model might correspond to the base BSIM model and a second model (with a unique name) is a macromodel that contains the base BSIM model and additional components (usually resistors and capacitors).

The motivation for creating the macromodel is to include estimates for resistor(s) and capacitor(s) due to interconnect traces. As an example, the definition of the gate location in a layout is totally subjective. Where exactly does the gate start?

The gate terminal of a the base BSIM MOS device model does not include the interconnect resistances and capacitances of the trace(s) to the physical gate. If you are creating a netlist based on the schematic view of a circuit, the impact of the traces to the physical gate are not included. Therefore, in a schematic view, the macro model is used to include at least some estimates of the gate trace impedances. When an RC based extracted view is created from the layout, the gate trace impedances are included in the netlist and hence the base BSIM model is called.

I think what you may have found are the capacitances defined for the macromodel in the folder "x_sub", and the capacitances of the base BSIM model in folder "slvtnfet_mmw_5t". Of course, I cannot be certain and might suggest you contact someone at the foundry who supplied the PDK or, if your company creates the PDK from the foundry PDK, someone in the modeling group that creates the PDK.

In case you do not have it, the basic BSIM-MG model for your technology is defined at the Berkeley site. To hopefully avoid my response from ending up in the spam folder, I cannot include the entire link as it will identify it as a non-Cadence site and flag it as spam. Hence, please copy each of the following and concatenate them to use in your favor browser.

bsim.berkeley.edu/

models/bsimimg/

Shawn