Create vias in a rectangular area

Hi Louis,

For the white flashing cross, there is probably a warning associated to the generated via (maybe a short), you might be able to find the root cause using in the Layout Toolbar "Verify" -> "Markers" -> "Explain" or "Find..."

For the ptArray issue, it's just that you are passing the variables names instead of their value

(As said in the error message, it tries to deduce points from the symbols x1, y1, etc. which are not numbers)

You should use list or range to provide them

ptArray=list( (list x1 y1) (list x1 y2) (list x2 y2) (list x2 y1))

ptArray=list( x1:y1 x1:y2 x2:y2 x2:y1 )

(Both solutions are valid as long as x1, y1, ... are numbers)

Another solution is to use backquote which

ptArray=`( (,x1 ,y1) (,x1 ,y2) (,x2 ,y2) (,x2 ,y1) )

list evaluates all arguments and you can quote some if you want

while backquote quotes all arguments and you can evaluate the ones you want using comma

Also, please note that you don't need to use list if all the elements are simple atoms (numbers, strings, ...)

ptArray=list('(0 27) '(20 27) '(20 37) '(0 37))

can be replaced by

ptArray='((0 27) (20 27) (20 37) (0 37))

Hope this helps

Aurélien

Dear Aurèlien,

 thanks for your suggestions which are working fine. Thanks a lot! The only issue is the persisting flashing white cross. I'm trying to attach here below the file with the report. The vias are basically done between two metal layers M2 and M3. A very simple condition. If I remove the via function, the white cross disappears. I hope you can help. 

I see also this error in the CIW window: Invalid bounding-box for a rectangle

I see the cross when I instantiate the cell.  

location: ("MY_PCELLS" "Microstrip_vers1" "layout")
reason:   (VIA-1010): Running the auto via command in area (0, 27) (0, 37) (20, 37) (20, 27).

location: ("MY_PCELLS" "Microstrip_vers1" "layout")
reason:   ********************************************************************************

location: ("MY_PCELLS" "Microstrip_vers1" "layout")
reason:   *                             Auto Via Statistics                              *

location: ("MY_PCELLS" "Microstrip_vers1" "layout")
reason:   * Area : (0, 27) (0, 37) (20, 37) (20, 27)                                     *

location: ("MY_PCELLS" "Microstrip_vers1" "layout")
reason:   * Run Time = 0.10 sec [cpu: 0.09 sec]                                          *

location: ("MY_PCELLS" "Microstrip_vers1" "layout")
reason:   * Total number of vias created: 1                                              *

location: ("MY_PCELLS" "Microstrip_vers1" "layout")
reason:   ********************************************************************************

location: ("MY_PCELLS" "Microstrip_vers1" "layout")
reason:   #

location: ("MY_PCELLS" "Microstrip_vers1" "layout")
reason:   # Summary

location: ("MY_PCELLS" "Microstrip_vers1" "layout")
reason:   ==================================================================================================================

location: ("MY_PCELLS" "Microstrip_vers1" "layout")
reason:   | Stack |  Metal Overlaps   |      Via      |    Initial Overlaps     |        Final Results        |  Percent   |

location: ("MY_PCELLS" "Microstrip_vers1" "layout")
reason:   | Depth |  Bottom - Top     |               |   Total   | Unconnected | Newly Connected | Connected |            |

location: ("MY_PCELLS" "Microstrip_vers1" "layout")
reason:   ------------------------------------------------------------------------------------------------------------------

location: ("MY_PCELLS" "Microstrip_vers1" "layout")
reason:   |   1   |      M2 - M3      |     VIA2      |         1 |           1 |               1 |         1 |   0 -> 100 |

location: ("MY_PCELLS" "Microstrip_vers1" "layout")
reason:   ------------------------------------------------------------------------------------------------------------------

location: ("MY_PCELLS" "Microstrip_vers1" "layout")
reason:   |                 Totals                    |         1 |           1 |               1 |         1 |   0 -> 100 |

location: ("MY_PCELLS" "Microstrip_vers1" "layout")
reason:   ==================================================================================================================

--> Partial solution

After searching basically all the forum entries for the GenerateViainArea Function, I've found this one: community.cadence.com/.../mute-viagenerateviasinarea-echo-off-verbose-printf

which I've tried  and it worked fine to remove the white flashing cross after the procedure I'm using to create the via is loaded in SKILL IDE: 

myViaOptions->automatic->printStatisticsReport=nil

I was happy but, as I try to run EMX, I get the error: "strmount failed streaming out cell". 

I've run Lint of the code and I see this error: 

Variables used as both global and local:

pcCellView

From what I could see, pcCellView is the current PCELL being created through the .il SKILL file. 

pcCellView is an internal variable automatically created by pcDefinePCell. pcCellView contains the dbID (database identification) of the cell you are creating. Within the body of your Pcell code, use the pcCellView variable as the cellview identifier for which you create objects. 

Interestingly, I see the white flashing cross when I open Cadence and the cell. As I load the .il code which is generating it, the white flashing cross disappears. 

Any help would be extremely appreciated. 

In the hope to get a feedback, I'm reporting here the code I'm using:

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

pcDefinePCell(

list(ddGetObj("MY_PCELLS") ; target library

"Via_vers2" ; target cell

"layout") ; target view

(

(Strip float(20.1))

)

let(

; get the layer info from the techfile

tfId = techGetTechFile(pcCellView)

/* Microstrip ground down*/

fig=dbCreateRect(

pcCellView ; cell reference

list("M2" "drawing") ; layer

list(

0:0

Strip:Strip)

); fig

tfId = techGetTechFile(pcCellView)

constraintGroupId=cstFindConstraintGroupIn(tfId "default")

viaOpts=viaGetViaOptions(constraintGroupId)

viaOpts~>createInRoute = nil

viaOpts~>automatic~>printStatisticsReport=nil

x1=0

y1=0

x2 =Strip

y2 =Strip

ptArray=`( (,x1 ,y1) (,x1 ,y2) (,x2 ,y2) (,x2 ,y1) )

fig=viaGenerateViasInArea(pcCellView ptArray viaOpts ?topAndBottomLayers list("M2" "M9V"))

) ; let

); fun

I get the correct layout:

But I also get the "strmount failed..." error when I try to run EMX simulations.

I would be very grateful if someone can help.

In the hope to get a feedback, I'm reporting here the code I'm using:

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

pcDefinePCell(

list(ddGetObj("MY_PCELLS") ; target library

"Via_vers2" ; target cell

"layout") ; target view

(

(Strip float(20.1))

)

let(

; get the layer info from the techfile

tfId = techGetTechFile(pcCellView)

/* Microstrip ground down*/

fig=dbCreateRect(

pcCellView ; cell reference

list("M2" "drawing") ; layer

list(

0:0

Strip:Strip)

); fig

tfId = techGetTechFile(pcCellView)

constraintGroupId=cstFindConstraintGroupIn(tfId "default")

viaOpts=viaGetViaOptions(constraintGroupId)

viaOpts~>createInRoute = nil

viaOpts~>automatic~>printStatisticsReport=nil

x1=0

y1=0

x2 =Strip

y2 =Strip

ptArray=`( (,x1 ,y1) (,x1 ,y2) (,x2 ,y2) (,x2 ,y1) )

fig=viaGenerateViasInArea(pcCellView ptArray viaOpts ?topAndBottomLayers list("M2" "M9V"))

) ; let

); fun

I get the correct layout:

But I also get the "strmount failed..." error when I try to run EMX simulations.

I would be very grateful if someone can help.

I'm still struggling with this problem. 

I've noticed that when opening a layout including the vias created with the previously described pcell (Via_vers2), a white flashing cross appears. The CWS reports:

Pcell evaluation for MY_PCELLS/Via_vers2/layout generated information. See layer/purpose "marker/error" shape with property "drcWhy" for description. You can get more details from file /tmp/_pcEvalac3585.

The file pcEvalac3585 contains:

Loading via.cxt

The marker error layer shows a rectangle covering the via areas. I would be really grateful if someone can help. 

Apparently, the issue is caused by the following lines of code: 

cons=cstGetDefaultConstraintGroupName(pcCellView "Via"); "tech:virtuosoDefaultSetup(cmos065_tech)"
constraintGroupId=cstFindConstraintGroupIn(tfId "virtuosoDefaultSetup")
viaOpts=viaGetViaOptions(constraintGroupId)

As I try to extract via options, the streamout error appears. If I try to run this sequence step by step in the CIW, I get this error:

*** Error in routine eval:
Message: *Error* eval: unbound variable - viaOpt
Entering new debug toplevel due to error:

By inspecting viaOpt I get: 

viaOpts~>??
(createInRoute t createAsROD nil rodName
"" automatic via:0x3ccb90f0 constraintGroupSetup via:0x3ccb9030
)

I hope you can help. 

Hi,

It seems that you have a typo between viaOpts and viaOpt...

Cheers,

Aurélien

Also, from what I sent you in direct messages, viaGenerateViasAtPoint should not be used in pCell code but it also includes viaGenerateViaOptions, etc.

Here's the reference (For the clarity of this thread)

From this article  AUTOVIA: SKILL API for generating vias in layout which does not require Create Via form interaction. viaGenerateViasAtPoint function needs 12 GXL tokens or EAD or EXL license and is not supported in pcell code - gives pcellEvalFailed during strmout

You can see

In IC6.1.7.500.7 and ICADV12.2.500.7 a new set of via generation SKILL API's has been released which helps with autovia creation. 

NOTE: These functions are not supported in a pcell code i.e. within pcDefinePCell. Using them in pcell may result in error pcell evaluation failure during Stream Out or Xstream Out or GDS creation:

In addition, you should read this chapter in the documentation: Safety Rules for Creating SKILL Pcells

Andrew