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Problem importing spice netlist

GS202511058825

This question is for IC618.

I am trying to import a simple AND gate into my library as a schematic but I get the following error: 

ERROR (SPICEIN_GUI-25): Spice In import failed or is incomplete. Check logfile 'spiceIn.log' for errors.

However, the logfile cuts off in the middle of creating the schematic. This is also occurring for several other gates I've tried to import, but some of them import with no issues. I have already set up device mapping.

Here is the netlist:


.option scale=0.1u

.subckt AND2X1 VDD GND A Y B
M1000 Base_Cell_Single_Bool_3/a_55_24# VDD Y VDD pfet w=20 l=2
+ ad=100 pd=50 as=124 ps=52
M1001 Base_Cell_Single_Bool_3/a_55_n44# GND Y GND nfet w=16 l=2
+ ad=80 pd=42 as=96 ps=44
M1002 Y m1_7_25# VDD VDD pfet w=20 l=2
+ ad=0 pd=0 as=224 ps=102
M1003 Y m1_7_25# GND GND nfet w=16 l=2
+ ad=0 pd=0 as=96 ps=44
M1004 VDD B m1_7_25# VDD pfet w=20 l=2
+ ad=0 pd=0 as=124 ps=52
M1005 GND B Base_Cell_Single_Bool_0/a_55_n44# GND nfet w=16 l=2
+ ad=0 pd=0 as=96 ps=44
M1006 m1_7_25# A VDD VDD pfet w=20 l=2
+ ad=0 pd=0 as=0 ps=0
M1007 Base_Cell_Single_Bool_0/a_55_n44# A m1_7_25# GND nfet w=16 l=2
+ ad=0 pd=0 as=80 ps=42
C0 VDD GND 4.59fF
.ends

Here is the logfile:

===================
Spice In Log File
===================
Parameter file: /tmp/spiceInPo32970
Import Parameters:
Netlist file name: /home/srinivgu/Documents/ThesisResearch/Spice_Models_Hybrid/AND2X1.sp
Output library name: Hybrid
Output View Type: schematic
Schematic view name: schematic
Netlist view name: netlist_tmp
Reference Library List: NCSU_Devices_FreePDK45 Hybrid
Top cell: top
Device-mapping file name: /home/srinivgu/Documents/ThesisResearch/devicemap_hybrid
Master Cell for Ground: gnd
Schematic Generation parameter file: /tmp/schOpts_spiceInPo32970
Simulator: spectre
Output Simulator: spectre
paramCaseValue: default
Language: SPICE
Total number of files: 1.

Netlist File: /home/srinivgu/Documents/ThesisResearch/Spice_Models_Hybrid/AND2X1.sp.
Total number of Subckts: 1.

********
Created Hybrid.AND2X1:netlist_tmp
Created net VDD.
Created term VDD.
Created net GND.
Created term GND.
Created net A.
Created term A.
Created net Y.
Created term Y.
Created net B.
Created term B.

Total number of Insts: 9.

Inst: M1000
Created net 'Base_Cell_Single_Bool_3/a_55_24#'.
Found net 'VDD'.
Found net 'Y'.
Found net 'VDD'.
Created net 'pfet'.

Master Cell 'pfet' mapped to 'PMOS_VTL'.
Master Cellview: 'NCSU_Devices_FreePDK45.PMOS_VTL:symbol' found.
Created instance 'M1000'.
Created connection between net '

Parents
  • Andrew Beckett

    OK, I suspect the reason it's failing is because you've not mapped the capacitor (I had the same problem initially). There's no capacitor (as far as I can see) in the NCSU FreePDK45, so I added analogLib as a reference library as well and defined the mapping:

    -- Device Mapping file generated from SpiceIn GUI
    devSelect := nfet NMOS_VTL

    devSelect := pfet PMOS_VTL

    devSelect := capacitor cap

    The file truncation doesn't help diagnose this, and it seems that it doesn't like the "/" character in the net names:

    *WARNING* (DB-270000): dbFindNetByName: Invalid character '/' in input name: Base_Cell_Single_Bool_3/a_55_24#.
    *WARNING* (DB-270000): dbCreateNet: Invalid character '/' in input name: Base_Cell_Single_Bool_3/a_55_24#.
    *WARNING* (DB-270000): dbFindNetByName: Invalid character '/' in input name: Base_Cell_Single_Bool_3/a_55_n44#.
    *WARNING* (DB-270000): dbCreateNet: Invalid character '/' in input name: Base_Cell_Single_Bool_3/a_55_n44#.
    *WARNING* (DB-270000): dbFindNetByName: Invalid character '/' in input name: Base_Cell_Single_Bool_0/a_55_n44#.
    *WARNING* (DB-270000): dbCreateNet: Invalid character '/' in input name: Base_Cell_Single_Bool_0/a_55_n44#.
    *WARNING* (DB-270000): dbFindNetByName: Invalid character '/' in input name: Base_Cell_Single_Bool_0/a_55_n44#.

    (this doesn't show up in the log, but I saw it when running spiceIn from the command line). I changed all the "/" characters in the net names to (say) double underscore "__" and then it reported the missing capacitor mapping:

    ERROR (SPICEIN-24): Spice In did not find the symbol view of the master cell 'capacitor' of the instance
    'C0' in the subcircuit 'AND2X1'. Specify the reference library that has the symbol
    view of the master cell, or use device-mapping to map 'capacitor' to a different cell.
    Some device mapping file examples for commonly used components while importing
    a spice netlist include:
    devselect := resistor res
    devselect := capacitor cap
    devselect := inductor ind
    devselect := mutual_inductor mind

    with the capacitor mapping shown at the top of my reply, it gives a full log file and succeeds.

    There's an old Cadence Change Request #559787 which talks about the log truncating when such a character is found (and a few duplicates). Sadly it hasn't been fixed (the request is to map the names that aren't legal in Virtuoso).

    Andrew

Reply
  • Andrew Beckett

    OK, I suspect the reason it's failing is because you've not mapped the capacitor (I had the same problem initially). There's no capacitor (as far as I can see) in the NCSU FreePDK45, so I added analogLib as a reference library as well and defined the mapping:

    -- Device Mapping file generated from SpiceIn GUI
    devSelect := nfet NMOS_VTL

    devSelect := pfet PMOS_VTL

    devSelect := capacitor cap

    The file truncation doesn't help diagnose this, and it seems that it doesn't like the "/" character in the net names:

    *WARNING* (DB-270000): dbFindNetByName: Invalid character '/' in input name: Base_Cell_Single_Bool_3/a_55_24#.
    *WARNING* (DB-270000): dbCreateNet: Invalid character '/' in input name: Base_Cell_Single_Bool_3/a_55_24#.
    *WARNING* (DB-270000): dbFindNetByName: Invalid character '/' in input name: Base_Cell_Single_Bool_3/a_55_n44#.
    *WARNING* (DB-270000): dbCreateNet: Invalid character '/' in input name: Base_Cell_Single_Bool_3/a_55_n44#.
    *WARNING* (DB-270000): dbFindNetByName: Invalid character '/' in input name: Base_Cell_Single_Bool_0/a_55_n44#.
    *WARNING* (DB-270000): dbCreateNet: Invalid character '/' in input name: Base_Cell_Single_Bool_0/a_55_n44#.
    *WARNING* (DB-270000): dbFindNetByName: Invalid character '/' in input name: Base_Cell_Single_Bool_0/a_55_n44#.

    (this doesn't show up in the log, but I saw it when running spiceIn from the command line). I changed all the "/" characters in the net names to (say) double underscore "__" and then it reported the missing capacitor mapping:

    ERROR (SPICEIN-24): Spice In did not find the symbol view of the master cell 'capacitor' of the instance
    'C0' in the subcircuit 'AND2X1'. Specify the reference library that has the symbol
    view of the master cell, or use device-mapping to map 'capacitor' to a different cell.
    Some device mapping file examples for commonly used components while importing
    a spice netlist include:
    devselect := resistor res
    devselect := capacitor cap
    devselect := inductor ind
    devselect := mutual_inductor mind

    with the capacitor mapping shown at the top of my reply, it gives a full log file and succeeds.

    There's an old Cadence Change Request #559787 which talks about the log truncating when such a character is found (and a few duplicates). Sadly it hasn't been fixed (the request is to map the names that aren't legal in Virtuoso).

    Andrew

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