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Designing for low power

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OK, since it's an area I have a bit of interest in, how about a couple of general questions to kick things off:

How many people in here are actually designing for "low power"?

What techniques are you using?

CD


Originally posted in cdnusers.org by crispy_duck
Parents

  • Hi Crispy Duck,

    Some simple starters. See how many people make these mistakes:

    1. Spare gate inputs should be tie to high or low to reduce leakage
    2. decap cell has leakage; filler cell don't
    3. a FF with async-set and Q/Q- can have 0.001nW less leakage than a FF without async set/reset and Q output only. However the former is 30% bigger in area, and don't need tie cell. If you ask the synthesis tool to optimise leakage, which FF do you think the tool will use?

    Regards,
    Eng Han


    Originally posted in cdnusers.org by EngHan
Reply

  • Hi Crispy Duck,

    Some simple starters. See how many people make these mistakes:

    1. Spare gate inputs should be tie to high or low to reduce leakage
    2. decap cell has leakage; filler cell don't
    3. a FF with async-set and Q/Q- can have 0.001nW less leakage than a FF without async set/reset and Q output only. However the former is 30% bigger in area, and don't need tie cell. If you ask the synthesis tool to optimise leakage, which FF do you think the tool will use?

    Regards,
    Eng Han


    Originally posted in cdnusers.org by EngHan
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