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Designing for low power

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OK, since it's an area I have a bit of interest in, how about a couple of general questions to kick things off:

How many people in here are actually designing for "low power"?

What techniques are you using?

CD


Originally posted in cdnusers.org by crispy_duck
Parents

  • My personal favourites:

    1) Failing to clamp outputs from a powered-domain into an unpowered one when the library has diode-protection to Vdd in all cells (Oh look, we're powering the core via a single wire!)
    2) Rebuffering feed-through nets inside a chiplet which has all its power turned-off (Oh, where has our interrupt gone???)
    3)Passing a clock from one domain to another and back, then discovering that the timing alters with respect to a path that is kept in the first domain (Why does our chip fail when we alter the voltages??)

    I could go on, but I'd like to retain the illusion that I'm competent at this sort of stuff ;-)

    CD


    Originally posted in cdnusers.org by crispy_duck
Reply

  • My personal favourites:

    1) Failing to clamp outputs from a powered-domain into an unpowered one when the library has diode-protection to Vdd in all cells (Oh look, we're powering the core via a single wire!)
    2) Rebuffering feed-through nets inside a chiplet which has all its power turned-off (Oh, where has our interrupt gone???)
    3)Passing a clock from one domain to another and back, then discovering that the timing alters with respect to a path that is kept in the first domain (Why does our chip fail when we alter the voltages??)

    I could go on, but I'd like to retain the illusion that I'm competent at this sort of stuff ;-)

    CD


    Originally posted in cdnusers.org by crispy_duck
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