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Leakage power vs DFM?

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Hi,

Recently EE Times published an article about leakage power vs. yield. (http://eetimes.com/news/latest/showArticle.jhtml?articleID=172303036)

I thought it was interesting, because we usually think in terms of leakage power vs. performance, or leakage power contributing to total power, affecting package cost or battery life.

What do you think about the article? Are you also seeing a definable correlation between leakage power and yield?

Thanks.


Originally posted in cdnusers.org by wtan

  • The word "yield" used to mean functional yield - chips that functioned correctly. A functional failure is a chip that does not behave as it should.

    However, when process geometries drop below 100nm, another kind of failure becomes important - "parametric" failures - chips that function correctly, but fail to meet timing and power specifications.

    Leakage power is one of the main causes of parametric failure. Below 100nm, more chips fail because of timing/power than functionality. Parametric yield becomes more important than functional yield.

    So, leakage power is a primary factor in determining parametric yield.


    Originally posted in cdnusers.org by cyi

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