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PVT corner for worst case power analysis

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Hello,

I am not sure about what PVT corner I should use for worst case power analysis. I have identified two things in LIB files which are affected by PVT corner selection and affects power analysis:

  • K_factors for internal and leakage power;

  • Transition time.

Temperature selection is ok! When we increase temperature we increase power consumption since both k_factors and transition time are directly proportional to temperature (power consumption of a cell depends on input transition time)

The problem is for process and voltage selection:

  • Transition time decreases when we increase operating voltage (inversely proportional), in contrast of k_factors. So, I should select low or high voltage for worst case power analysis?

  • Transition time increases when we increase process value (directly proportional), in contrast of k_factors. So, I should select low or high process for worst case power analysis?

Besides that, most of LIB files describes PVT corners only for STA and these corners are different for power analysis. So, it is needed define new corners in LIB files to perform worst case power analysis?

Anyone can help me?
Thanks in advance...

 


Originally posted in cdnusers.org by clsantos
Parents

  • I can certainly commiserate with you, my libraries are also setup for timing PVT points.

    Can I ask how accurate do you need your power estimate to be?

    In my experience, the inaccuracies in things like activity estimation, library data etc will tend to make the values measured with real silicon somewhat different to the pre-tapeout estimations (and even more different to RTL level estimation of power). What I do know however is that the relative saving of using a technique will be accurate between the estimation and the silicon.

    I know some tools allow values for P V & T to be set independent of the actual library fixed points, but I'm not sure if this is available in all Cadence tools.

    Chris


    Originally posted in cdnusers.org by Chris_Byham
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  • I can certainly commiserate with you, my libraries are also setup for timing PVT points.

    Can I ask how accurate do you need your power estimate to be?

    In my experience, the inaccuracies in things like activity estimation, library data etc will tend to make the values measured with real silicon somewhat different to the pre-tapeout estimations (and even more different to RTL level estimation of power). What I do know however is that the relative saving of using a technique will be accurate between the estimation and the silicon.

    I know some tools allow values for P V & T to be set independent of the actual library fixed points, but I'm not sure if this is available in all Cadence tools.

    Chris


    Originally posted in cdnusers.org by Chris_Byham
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