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PVT corner for worst case power analysis

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Hello,

I am not sure about what PVT corner I should use for worst case power analysis. I have identified two things in LIB files which are affected by PVT corner selection and affects power analysis:

  • K_factors for internal and leakage power;

  • Transition time.

Temperature selection is ok! When we increase temperature we increase power consumption since both k_factors and transition time are directly proportional to temperature (power consumption of a cell depends on input transition time)

The problem is for process and voltage selection:

  • Transition time decreases when we increase operating voltage (inversely proportional), in contrast of k_factors. So, I should select low or high voltage for worst case power analysis?

  • Transition time increases when we increase process value (directly proportional), in contrast of k_factors. So, I should select low or high process for worst case power analysis?

Besides that, most of LIB files describes PVT corners only for STA and these corners are different for power analysis. So, it is needed define new corners in LIB files to perform worst case power analysis?

Anyone can help me?
Thanks in advance...

 


Originally posted in cdnusers.org by clsantos
Parents

  • I am using simulation based analysis (with VCD files) because I think that is the most accurate analysis which is possible to perform using Encounter. Is it right?
    I know that any gate-level analysis will result in a power estimation somewhat different to measured values, but I think it is the best power estimation I can do at this design step. I intend to use this type of analysis to optimize power consumption once, as you have said, relative power savings will be valid in real silicon measurements.
    I tried overcome the problem of existing only PVT corners for timing in my LIB files by creating a new “dummy” LIB file just to specify power PVT corners. And it seems be ok!
    But my main problem is identify the right corner values for process and voltage to perform a safe power analysis. As I have stated in previous message, choosing best/worst values for voltage or process increases power through transition time but at the same time decreases power through k_factors, and vice-versa...
    So, it is better chose best or worst values for process and voltage to guarantee a safe power analysis?


    Originally posted in cdnusers.org by clsantos
Reply

  • I am using simulation based analysis (with VCD files) because I think that is the most accurate analysis which is possible to perform using Encounter. Is it right?
    I know that any gate-level analysis will result in a power estimation somewhat different to measured values, but I think it is the best power estimation I can do at this design step. I intend to use this type of analysis to optimize power consumption once, as you have said, relative power savings will be valid in real silicon measurements.
    I tried overcome the problem of existing only PVT corners for timing in my LIB files by creating a new “dummy” LIB file just to specify power PVT corners. And it seems be ok!
    But my main problem is identify the right corner values for process and voltage to perform a safe power analysis. As I have stated in previous message, choosing best/worst values for voltage or process increases power through transition time but at the same time decreases power through k_factors, and vice-versa...
    So, it is better chose best or worst values for process and voltage to guarantee a safe power analysis?


    Originally posted in cdnusers.org by clsantos
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