PVT corner for worst case power analysis

Simulation based analysis is by far the most accurate, but care is needed to ensure that you really have accurate use-cases for your block or chip in simulation.

For example, I'm heavily involved with SoC integration, and although my team has testcases for IP blocks in the chip, these are typically only stressing the interface so we can ensure the integration is correct. It is less common for us to run simulations stressing each IP to ensure that it is performing it's own internal functions correctly (really depends on the source and complexity of the IP: I might test a Uart to the fullest extent, but a DSP that has been used on other products may only have a brief interface test). Thus if I were to use these sims as a basis for power-analysis, I may or may not get an accurate picture of the power consumption. So I tend to have to base my analysis on statistical analysis.

As for which point to use for the actual analysis, yes I understand your problem. I don't think there is a right or wrong answer. I personally run my analysis at the worst-case timing PVT point, and don't worry if this is the worst power point. If I run all of my analysis at the same operating conditions, then the effect of design changes is surely valid. Also, since both my synthesis and layout tools are using this PVT to do optimisation for timing, then it makes sense to base all of my analysis here.

Of course, if you are trying to see what effect making the design [i]high-Vt and std Vdd[/i] compared to [i]low-Vt with reduced Vdd[/i], then you could well see "savings" which are caused by the different operating points.

You say that you've tried making dummy PVT points that match (suspected) power corners rather than timing corners. Can you run your analysis and tell us what difference P, V and T have on estimated dynamic and static power? My own gut feel is that the power increase caused by higher transition times will be less than that caused by higher voltages since power is just proportional to frequency, but is proportional to the square of the voltage.

Chris

Simulation based analysis is by far the most accurate, but care is needed to ensure that you really have accurate use-cases for your block or chip in simulation.

For example, I'm heavily involved with SoC integration, and although my team has testcases for IP blocks in the chip, these are typically only stressing the interface so we can ensure the integration is correct. It is less common for us to run simulations stressing each IP to ensure that it is performing it's own internal functions correctly (really depends on the source and complexity of the IP: I might test a Uart to the fullest extent, but a DSP that has been used on other products may only have a brief interface test). Thus if I were to use these sims as a basis for power-analysis, I may or may not get an accurate picture of the power consumption. So I tend to have to base my analysis on statistical analysis.

As for which point to use for the actual analysis, yes I understand your problem. I don't think there is a right or wrong answer. I personally run my analysis at the worst-case timing PVT point, and don't worry if this is the worst power point. If I run all of my analysis at the same operating conditions, then the effect of design changes is surely valid. Also, since both my synthesis and layout tools are using this PVT to do optimisation for timing, then it makes sense to base all of my analysis here.

Of course, if you are trying to see what effect making the design [i]high-Vt and std Vdd[/i] compared to [i]low-Vt with reduced Vdd[/i], then you could well see "savings" which are caused by the different operating points.

You say that you've tried making dummy PVT points that match (suspected) power corners rather than timing corners. Can you run your analysis and tell us what difference P, V and T have on estimated dynamic and static power? My own gut feel is that the power increase caused by higher transition times will be less than that caused by higher voltages since power is just proportional to frequency, but is proportional to the square of the voltage.

Chris