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PVT corner for worst case power analysis

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Hello,

I am not sure about what PVT corner I should use for worst case power analysis. I have identified two things in LIB files which are affected by PVT corner selection and affects power analysis:

  • K_factors for internal and leakage power;

  • Transition time.

Temperature selection is ok! When we increase temperature we increase power consumption since both k_factors and transition time are directly proportional to temperature (power consumption of a cell depends on input transition time)

The problem is for process and voltage selection:

  • Transition time decreases when we increase operating voltage (inversely proportional), in contrast of k_factors. So, I should select low or high voltage for worst case power analysis?

  • Transition time increases when we increase process value (directly proportional), in contrast of k_factors. So, I should select low or high process for worst case power analysis?

Besides that, most of LIB files describes PVT corners only for STA and these corners are different for power analysis. So, it is needed define new corners in LIB files to perform worst case power analysis?

Anyone can help me?
Thanks in advance...

 


Originally posted in cdnusers.org by clsantos
Parents

  • I used a small block of an rfid tag of 5Kgates operating at very low frequency (640KHz) and I tested these PVT combinations:

    Case 1: WORST extraction, HIGH temperature, HIGH voltage, BEST process => 1.2637e-01 mW
    Case 2: WORST extraction, HIGH temperature, LOW voltage, BEST process => 7.8231e-02 mW
    Case 3: WORST extraction, HIGH temperature, HIGH voltage, WORST process => 1.0015e-01 mw
    Case 4: WORST extraction, HIGH temperature, LOW voltage, WORST process => 6.4237e-02 mw

    Case 5: BEST extraction, LOW temperature, LOW voltage, WORST process => 5.3186e-02 m
    Case 6: BEST extraction, LOW temperature, HIGH voltage, WORST process => 8.3718e-02 mw
    Case 7: BEST extraction, LOW temperature, LOW voltage, BEST process => 6.9326e-02 mw
    Case 8: BEST extraction, LOW temperature, HIGH voltage, BEST process => 1.1280e-01 mw

    As you have said, both voltage and process have more influence on cell delay by k_factors than by the increase of transition times. So, I will use “Case 1” as PVT point to estimate the worst IR drop.

    Thanks,
    Cristiano.


    Originally posted in cdnusers.org by clsantos
Reply

  • I used a small block of an rfid tag of 5Kgates operating at very low frequency (640KHz) and I tested these PVT combinations:

    Case 1: WORST extraction, HIGH temperature, HIGH voltage, BEST process => 1.2637e-01 mW
    Case 2: WORST extraction, HIGH temperature, LOW voltage, BEST process => 7.8231e-02 mW
    Case 3: WORST extraction, HIGH temperature, HIGH voltage, WORST process => 1.0015e-01 mw
    Case 4: WORST extraction, HIGH temperature, LOW voltage, WORST process => 6.4237e-02 mw

    Case 5: BEST extraction, LOW temperature, LOW voltage, WORST process => 5.3186e-02 m
    Case 6: BEST extraction, LOW temperature, HIGH voltage, WORST process => 8.3718e-02 mw
    Case 7: BEST extraction, LOW temperature, LOW voltage, BEST process => 6.9326e-02 mw
    Case 8: BEST extraction, LOW temperature, HIGH voltage, BEST process => 1.1280e-01 mw

    As you have said, both voltage and process have more influence on cell delay by k_factors than by the increase of transition times. So, I will use “Case 1” as PVT point to estimate the worst IR drop.

    Thanks,
    Cristiano.


    Originally posted in cdnusers.org by clsantos
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