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PVT corner for worst case power analysis

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Hello,

I am not sure about what PVT corner I should use for worst case power analysis. I have identified two things in LIB files which are affected by PVT corner selection and affects power analysis:

  • K_factors for internal and leakage power;

  • Transition time.

Temperature selection is ok! When we increase temperature we increase power consumption since both k_factors and transition time are directly proportional to temperature (power consumption of a cell depends on input transition time)

The problem is for process and voltage selection:

  • Transition time decreases when we increase operating voltage (inversely proportional), in contrast of k_factors. So, I should select low or high voltage for worst case power analysis?

  • Transition time increases when we increase process value (directly proportional), in contrast of k_factors. So, I should select low or high process for worst case power analysis?

Besides that, most of LIB files describes PVT corners only for STA and these corners are different for power analysis. So, it is needed define new corners in LIB files to perform worst case power analysis?

Anyone can help me?
Thanks in advance...

 


Originally posted in cdnusers.org by clsantos
Parents


  • If you really want to find the worst power. You can probably measure it on 2 cycles with a VCD from an ATPG at speed test. This will try to toggle as many FFs as possible in your designs, ignoring protocols and everything else. Then take case 1 above and you probably have yourself in your worst case scenario. Actually you can probably make it even worst by using an overdrive voltage of the type that might be used to age the part during characterization. Then of course you have the question of what do I do with that? my guess is nothing as if you design to support that you will most likely explode your design constraints. (which is why a lot of people are working on different approach to reduce test power requirement without killing test time)

    Of course I agree with Chrys's statement which I believe give an accurate view of what is being done today with the exception of analyzing thing such as leakage power in stand by mode which may not be as important for your design but is crucial for some application (battery life anyone?).

    In my personal opinion the critical items of today's design regarding power are:

    1. Simulations providing realistic use case scenario. (note that 1 is not enough especially for SOC as various area of the design might be active at different time)
    2. Accurate IR drop backannotation and usage in STA/Power analysis tools (requires accurate modeling)
    3. Accurate glitch analysis.
    4. Signal EM analysis
    5. Good decap requirement prediction (in order to help with peak power requirement without killing leakage)
    6. Education of the whole management/Customer chain i.e. There is not a single power number for a chip it all depends on use scenario.

    Now I would love to hear about what you guys are doing for each of the problems above and also if anybody as looked at SSTA like approach to power analysis i.e. the chip is not in case 1 or case 2 above but in a combination of the various parameters.

    Thanks,
    Eric.


    Originally posted in cdnusers.org by evenditti
Reply


  • If you really want to find the worst power. You can probably measure it on 2 cycles with a VCD from an ATPG at speed test. This will try to toggle as many FFs as possible in your designs, ignoring protocols and everything else. Then take case 1 above and you probably have yourself in your worst case scenario. Actually you can probably make it even worst by using an overdrive voltage of the type that might be used to age the part during characterization. Then of course you have the question of what do I do with that? my guess is nothing as if you design to support that you will most likely explode your design constraints. (which is why a lot of people are working on different approach to reduce test power requirement without killing test time)

    Of course I agree with Chrys's statement which I believe give an accurate view of what is being done today with the exception of analyzing thing such as leakage power in stand by mode which may not be as important for your design but is crucial for some application (battery life anyone?).

    In my personal opinion the critical items of today's design regarding power are:

    1. Simulations providing realistic use case scenario. (note that 1 is not enough especially for SOC as various area of the design might be active at different time)
    2. Accurate IR drop backannotation and usage in STA/Power analysis tools (requires accurate modeling)
    3. Accurate glitch analysis.
    4. Signal EM analysis
    5. Good decap requirement prediction (in order to help with peak power requirement without killing leakage)
    6. Education of the whole management/Customer chain i.e. There is not a single power number for a chip it all depends on use scenario.

    Now I would love to hear about what you guys are doing for each of the problems above and also if anybody as looked at SSTA like approach to power analysis i.e. the chip is not in case 1 or case 2 above but in a combination of the various parameters.

    Thanks,
    Eric.


    Originally posted in cdnusers.org by evenditti
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