• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Digital Implementation
  3. Low Power tip of the Week: Special cells fro advanced low...

Stats

  • Locked Locked
  • Replies 0
  • Subscribers 90
  • Views 12753
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Low Power tip of the Week: Special cells fro advanced low power techniques

archive
archive over 18 years ago

One thing to note when designing for low power using advanced LP methodologies is: Make sure the library you are using has the required low power cells

Multiple supply voltage: Level shifter cells
Power shutoff: Isolation cells, power switch cells

Libraries for older process nodes (130nm and older) usually will not contain the cells above, so you might have to design them before you can use them.

Questions? Comment? Feel free to post!


Originally posted in cdnusers.org by wtan
  • Cancel

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information