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Clock nets in the design

vicky

Hi,

I would like to know what is the easiest way to get all the clock nets in the design using encounter. I do know that we can do it using saveClockNets which needs a clock tree spec file to be readin. I would like to  know if there is a much simpler way to do it may be using some get_nets command.

 

Regards

Vicky 

  • Rajesh Vembu

    Hi Vicky,

    saveClockNets command is supposed to work only after CTS is done. If you use this command pre-CTS to get a list of nets in the clock path, you might not get the desired results.

    Looks like there's a limit on the fanout of the net that gets reported if you use the command pre-CTS.

    Hope this helps.

    Regards

    Rajesh

  • vicky

    HI Rajesh,

    I am working on a preCTS db and would like to know how to get the list aof all the clock nets.

     

    Regards

    Vicky 

  • BobD
    Hi Vicky!

    This area is often confusing since there are lots of different types of ways/things that people might consider "clocks or not clocks". They are:

    1) An object in the design (net, pin or port) was found to be clock from a timing perspective. The timing constraints are loaded which includes "create_clock" statements, timing analysis is performed, the create_clock statements propagate from net to net and then some objects along that tracing are considered "clock" or not.

    2) A marking in the .lib declares something to be a clock or not.

    3) An object in the design (net, pin, or port) was found to be part of a clock tree that's been physically built and has a DEF marking on the nets declaring them to be "clock".

    Hopefully we now have a baseline for discussing whether things are clocks or not.  It sounds like what you're looking for (since you say that you don't want to load a clock tree spec file) is a list of nets that are considered "clock" from a timing perspective (ie, case "1" above).  The easiest way I can recommend to get this list of nets is using dbGet.

    First, time the design so that the nets are marked in the db as clock or not clock:
    encounter> timeDesign -prePlace

    Then, use dbGet as follows:
    encounter> dbGet [dbGet -p top.nets.isClock 1].name   
    DTMF_INST/m_spi_clk DTMF_INST/m_clk DTMF_INST/m_rcc_clk DTMF_INST/m_digit_clk DTMF_INST/TDSP_DS_CS_INST/n_28 DTMF_INST/TDSP_DS_CS_INST/n_30

    Some other things to consider:

    1) We do have a "get_nets" command within SoC-E, *but* it doesn't offer an "is_clock" marking on nets.

    2) The "is_clock" marking that we see on pins (ie, "get_property [get_pins i0/CK] is_clock") is a .lib marking (ie, of type "2" above), *not* the affect of SDCs that have influenced whether things are clock or not.

    Hope this is helpful,
    Bob

     
  • Nataraja G
    Hi Bob , when we load the design dbget top.nets.isClock 1 , doesn't return any clock nets but after timeDesign the nets are marked as you just mentioned above . my design is huge 6M-instances timeDesign itself is killing all the time Apart from timeDesign can't we do anything to get these clock net markings ? Regards Nataraja G

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