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NanoRoute: DRC / LVS issues

kulprashant

Hi,

I have completed the routing using Nanoroute and the in the summary report, there are no LVS violation and few DRC violation(~50).

I saved the design and then from GUI, i check the DRC with all option (command : verifyGeometry with default option), then i was shocked by looking towards results, there thousand of violations and lot of process antenna violation(~100).

1, how it is possible? nanoroute has not dumped correct report or is thier any other issues?

2. In DRC, i have checked, there are similar violation (almost all are same) and the DRC errors are spacing violation with same net?

                                 exa: spacing vioaltion : metal: M3  actual =0.5   min =0.7

what is meaning of this and how to solve this type of issue (same type of violation with M2 & M1).

3. I found some max transition and max fanout violation, how to solve these violation at this stage? (because solving these vioaltion nothing but adding or sizing the buffers at placement level, it means  i have to do once again CTS and routing ) or any other method to solve or ecos??

Thanks & Regards,

Kul   

Parents

  • Hi Kari,

    Thanks for your valuable suggestion.

    1. i have given two tech lef fiiles and there is different spacing rule for the same net exa: 

    samenet (metal 3) spacing 0.7 (in one file ) & 0.5(other file), so thats why i was getting the same net violation.

     2. For Antenna violation , it has cleared all except 2 violation and it is showing violation like

      Process antenna report created by VERIFY ANTENNA.

    EEPROM_DO_eep0[3] (2)
      u_eeprom_dft_mux/U510  (mx22_b) I1
    [1]    metal3:  Area:  303.68  S.Area:  729.65  G.Area:    0.70  D.Area:    0.00
                                      CAR:  454.19   Ratio:  300.00       (C.Area)
    EEPROM_DO_eep2[3] (2)
      u_eeprom_dft_mux/U851  (mx22_b) I0
    [1]    metal3:  Area:  292.80  S.Area:  707.62  G.Area:    0.70  D.Area:    0.00
                                      CAR:  422.65   Ratio:  300.00       (C.Area)

    Total number of process antenna violations: 2
       Number of pins violated: 2
       Number of nets violated: 2

    -- what is workaround this because again these violation on Metal3 (max layer) and i have specified tool to add the ANTENNA cells and  i cant do the metal hogging for this.

    please suggest.

    3. Actually after CTS, i have solved hold violation manually because tool was adding lot of buffers (3000) in the optimization, so i did manually and i checked only hold time and i have not checked for setup and DRV checks and directly proceed for the routing.

    then i realize that may be cause, after fixing hold vioaltion, i did the refine placement and then check for the setup & DRV vioaltion there i found lot of DRV violation with setup and then i optimized the design only setup & DRV checks by tool then it clears all the violation and i checked for the hold also. there were no hold violation. fianlly i did routing.

    is it correct way of doing ?? may be i am doing wrong way or putting extra efforts? any other method because i dont know the eco flow, can you suggest any smoothen alternate way?

    Please suggest.

     

    Thanks & Regards,

    Kul

Reply

  • Hi Kari,

    Thanks for your valuable suggestion.

    1. i have given two tech lef fiiles and there is different spacing rule for the same net exa: 

    samenet (metal 3) spacing 0.7 (in one file ) & 0.5(other file), so thats why i was getting the same net violation.

     2. For Antenna violation , it has cleared all except 2 violation and it is showing violation like

      Process antenna report created by VERIFY ANTENNA.

    EEPROM_DO_eep0[3] (2)
      u_eeprom_dft_mux/U510  (mx22_b) I1
    [1]    metal3:  Area:  303.68  S.Area:  729.65  G.Area:    0.70  D.Area:    0.00
                                      CAR:  454.19   Ratio:  300.00       (C.Area)
    EEPROM_DO_eep2[3] (2)
      u_eeprom_dft_mux/U851  (mx22_b) I0
    [1]    metal3:  Area:  292.80  S.Area:  707.62  G.Area:    0.70  D.Area:    0.00
                                      CAR:  422.65   Ratio:  300.00       (C.Area)

    Total number of process antenna violations: 2
       Number of pins violated: 2
       Number of nets violated: 2

    -- what is workaround this because again these violation on Metal3 (max layer) and i have specified tool to add the ANTENNA cells and  i cant do the metal hogging for this.

    please suggest.

    3. Actually after CTS, i have solved hold violation manually because tool was adding lot of buffers (3000) in the optimization, so i did manually and i checked only hold time and i have not checked for setup and DRV checks and directly proceed for the routing.

    then i realize that may be cause, after fixing hold vioaltion, i did the refine placement and then check for the setup & DRV vioaltion there i found lot of DRV violation with setup and then i optimized the design only setup & DRV checks by tool then it clears all the violation and i checked for the hold also. there were no hold violation. fianlly i did routing.

    is it correct way of doing ?? may be i am doing wrong way or putting extra efforts? any other method because i dont know the eco flow, can you suggest any smoothen alternate way?

    Please suggest.

     

    Thanks & Regards,

    Kul

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