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NanoRoute: DRC / LVS issues

kulprashant

Hi,

I have completed the routing using Nanoroute and the in the summary report, there are no LVS violation and few DRC violation(~50).

I saved the design and then from GUI, i check the DRC with all option (command : verifyGeometry with default option), then i was shocked by looking towards results, there thousand of violations and lot of process antenna violation(~100).

1, how it is possible? nanoroute has not dumped correct report or is thier any other issues?

2. In DRC, i have checked, there are similar violation (almost all are same) and the DRC errors are spacing violation with same net?

                                 exa: spacing vioaltion : metal: M3  actual =0.5   min =0.7

what is meaning of this and how to solve this type of issue (same type of violation with M2 & M1).

3. I found some max transition and max fanout violation, how to solve these violation at this stage? (because solving these vioaltion nothing but adding or sizing the buffers at placement level, it means  i have to do once again CTS and routing ) or any other method to solve or ecos??

Thanks & Regards,

Kul   

Parents

  •  Hi Kari,

    Thanks for your valuable suggestions.

    Actually i have gien the antenna cell name as "ANTENNA" and it was not taking tthis option (in my library there is no antenna cell), so i changing the option in the nanoroute (only insert the diode option) and run the nanoroute then it cleans all antenna violation and some other DRC violation cleaned manually.

    now the databse is clean and started working on calibre checks (DRC/LVS) using caliber and i have cleaned all DRC violation.

    while running LVS, i am getting lot of violations (missing nets violation), i have given the input like

    1. i dont have spice format file to give input, so i dumped verilog file from layout database and given input the tool and the GDS database. calibre has verlog translator option, here i have given ".cdl" file, instead of spice format libraries and run the command, and it is showing lot of missing nets vioaltion.

    I thoght there may be netlist problem and i tried different command to dump the netlist and i got different results in caliber  

    1. saveNetlist design_db/backend.lvs.v -excludeLeafCell -includePowerGround

    2. saveNetlist design_db/backend.lvs.v -includeLeafCell -includePowerGround

    2. saveNetlist design_db/backend.lvs.v -phy

    3. saveNetlist design_db/backend.lvs.v  

    which one is the correct format or command to dump the verilog netlist for LVS??

    we are checking on caliber dabase option not on heirarical mode and i tried to convert this verlog file into spice format by using following command:

     v2lvs -v backend.lvs.v -s library.spi -o bakend.spice > v2lvs.log

    there is license issue for this command.

    i used ".cdl" files as explained above, verilog library files are necessery for these conversion?

    any command which converts verlilog into spice format using ".cdl" library file.

     

    Thanks & Regards,

    Kul

     

     

     

Reply

  •  Hi Kari,

    Thanks for your valuable suggestions.

    Actually i have gien the antenna cell name as "ANTENNA" and it was not taking tthis option (in my library there is no antenna cell), so i changing the option in the nanoroute (only insert the diode option) and run the nanoroute then it cleans all antenna violation and some other DRC violation cleaned manually.

    now the databse is clean and started working on calibre checks (DRC/LVS) using caliber and i have cleaned all DRC violation.

    while running LVS, i am getting lot of violations (missing nets violation), i have given the input like

    1. i dont have spice format file to give input, so i dumped verilog file from layout database and given input the tool and the GDS database. calibre has verlog translator option, here i have given ".cdl" file, instead of spice format libraries and run the command, and it is showing lot of missing nets vioaltion.

    I thoght there may be netlist problem and i tried different command to dump the netlist and i got different results in caliber  

    1. saveNetlist design_db/backend.lvs.v -excludeLeafCell -includePowerGround

    2. saveNetlist design_db/backend.lvs.v -includeLeafCell -includePowerGround

    2. saveNetlist design_db/backend.lvs.v -phy

    3. saveNetlist design_db/backend.lvs.v  

    which one is the correct format or command to dump the verilog netlist for LVS??

    we are checking on caliber dabase option not on heirarical mode and i tried to convert this verlog file into spice format by using following command:

     v2lvs -v backend.lvs.v -s library.spi -o bakend.spice > v2lvs.log

    there is license issue for this command.

    i used ".cdl" files as explained above, verilog library files are necessery for these conversion?

    any command which converts verlilog into spice format using ".cdl" library file.

     

    Thanks & Regards,

    Kul

     

     

     

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