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NanoRoute: DRC / LVS issues

kulprashant

Hi,

I have completed the routing using Nanoroute and the in the summary report, there are no LVS violation and few DRC violation(~50).

I saved the design and then from GUI, i check the DRC with all option (command : verifyGeometry with default option), then i was shocked by looking towards results, there thousand of violations and lot of process antenna violation(~100).

1, how it is possible? nanoroute has not dumped correct report or is thier any other issues?

2. In DRC, i have checked, there are similar violation (almost all are same) and the DRC errors are spacing violation with same net?

                                 exa: spacing vioaltion : metal: M3  actual =0.5   min =0.7

what is meaning of this and how to solve this type of issue (same type of violation with M2 & M1).

3. I found some max transition and max fanout violation, how to solve these violation at this stage? (because solving these vioaltion nothing but adding or sizing the buffers at placement level, it means  i have to do once again CTS and routing ) or any other method to solve or ecos??

Thanks & Regards,

Kul   

Parents

  • Hi Kul,

    I'm glad you got your LVS working!

    It sounds like your metal fill works well too. Are you sure you even need via fill for your technology? I have never had to add via fill to a design. Do you have DRC errors saying your via layer density is too low?

    Filler cells are for continuing wells, std cell rails, etc. Metal fill is to achieve a minimum metal layer density across the whole chip. It's usually checked by stepping a check-box of a certain size across the chip and making sure the density in each check box meets the required percentage. You can also have max density errors in some technologies (too much metal).

    I don't have any links to white papers on these topics, so I hope my explanations are of some help.

    - Kari

Reply

  • Hi Kul,

    I'm glad you got your LVS working!

    It sounds like your metal fill works well too. Are you sure you even need via fill for your technology? I have never had to add via fill to a design. Do you have DRC errors saying your via layer density is too low?

    Filler cells are for continuing wells, std cell rails, etc. Metal fill is to achieve a minimum metal layer density across the whole chip. It's usually checked by stepping a check-box of a certain size across the chip and making sure the density in each check box meets the required percentage. You can also have max density errors in some technologies (too much metal).

    I don't have any links to white papers on these topics, so I hope my explanations are of some help.

    - Kari

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