senthesize sub-module

Hi all,

I want to synthesize a design with RC but with different constraints for different blocks. The top-level includes memory and analogue models and the digital part. I want to keep the interface for all the blocks in the top-level even when they are unconnected. For this I set this attribute and it works fine: set_attribute write_vlog_unconnected_port_style  full.

But some of the sub-modules in the digital block have constant inputs (connected to 0 or 1). For these blocks I would like that the RC removes the constant input port, propagate the constant and optimizes the logic. Currently it does not do that -maybe- because of the changing the above attribute. On the other hand when I try to do a synthesis for sub-blocks it fails since it cannot find the sub-design. I use the following command to synthesis a sub-module with name top_dig_mod1:

synthesize  -to_generic  /designs/cai_kll_beaver_top/subdesigns/top_dig_mod1

Any idea how to do this!

Thank you for your comments in advance!

Regards,

Masoud