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ECO Flow with the Clock Gating Flow

During clock gating, all the synchronous load enabled registers are going to get gated clock. If suppose, during ECO, if you want to make one synchronous load enable flop as a normal flop, then the clock has to reach the flop, without going through the ICG element. Do you have any recommendations on CTS or implementation side, in this kind of a scenario?

Originally posted in cdnusers.org by gukumar

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