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Manual pin placement: short errors at Floorplan stage

kulprashant

Hi,

while importing the design, i have loaded the pin information file (io assignment file) as per my requirement in the cadence rquired proper format, while reading it will not show any error, but  after power roting when i verified the design (verifyGeometry) then it showing 1000 wiring vioaltions and again continued placement and after placement that vioaltions are converted into the short violations.

please let me know how to do manual io(pin) assignment or any standard flow for IO (pin) placement should be follow so that i should not get any errors.

Note:

1. In automatic placement (placement stage), there are no errors for the pin placement

2. I have made only one change in the manual io assignment file ie pin location (except this every thing is same).

please suggest.

Thanks & Regards,

Kul 

  •  Kul,

    Could you post a picture of one of the violations?

    - Kari 

  • Hi Kari,

    Actually these violations are cleaned in the after routing.

    The violations are present on the pin just cross X mark on all the pins, I will send the picture for the same.I am working on digital block and this block goes in the Analog chip. In power planning I have created the power pins at end of the power straps in power strap creation (addStripe). But top level they don’t want the pins instead of this they want to increase the metal width of the core power rings and just connect the straps to the core power rings.I think due to this I will get the IR drop violations.How to connect or create the one or more power pins to place manually at required locations.How to copy a cell or wire in the encounter layout, what is command and how to bring all these editing attributes on the encounter menu (sorry for this query)I am using soc encounter version 6.2.Thanks & Regards,

    Kul

  • Hi Kul,

    I'm not sure I understand what your analog guys want the power to look like, or what your IR-drop concerns are. Could you draw or post a picture?

    For creating power pins manually at a specified location, use the command createPGPin.

    As for copying a cell, I'm not sure what you're trying to accomplish. To copy a wire, you can use the wire editor GUI:

    • hit "e" to bring up the wire editing form
    • select the wire you want to duplicate
    • click on the "duplicate selected wires" icon on the bottom of the form (3rd from the left in 7.1 - if you hold your mouse over the icon, a pop-up will tell you what it is)
    • the duplicate wire is right on top of the original, so it will look like nothing happened. Select the wire again and move it, and you will see that the original stays where it was and you have moved the copy.

    Hope that helps!

     - Kari

  •  Hi kari, thanks for the reply.

    Actually i have misunderstood the dupicate command & as u mentioned i was not able to see the duplicate wire to move the other place.

    Normally for block level i use to while creating the power strap, i use to crate power pins at the boundary

     addStripe -extend_to design_boundary -block_ring_top_layer_limit metal3...............

    In the present design there are lot of pins placed on the bottom side of the core, so some of the pins are coming under power strips.

    so my analog engineer doesnt want to power pins at the boundary, so that it will not create any problem for pin placement (signal pin)..

    to avoid this i have to create the power strips upto the core power rings only as shown in figure and i will create only one pair of VDD /VSS pin manually and which supplies power to the whole design.

    for this i have to increase the core power ring widths on all the side.

    due to only one pin (VDD /VSS) in the design, it doesnot effect the IR drop ??? 

    Regards,

    Prashant

     

  • Hi Prashant,

     Normally, we avoid placing block pins under power stripes. When creating a block in the top-down partitioning flow, this is easy - you just turn on the switches to make sure pins don't get placed under stripes. When creating a block from the bottom up, it's not as easy I guess. I don't know how big the block is or how many pins we're talking about, but is moving the pins out from under stripes by hand an option? 

    Your concern about IR drop is valid! If you only have power coming into your block from one location, as opposed to all the stripes connecting at the next level, then it certainly could be an issue. If your block is pretty small, it may not be. It's hard to say without knowing the design. Will you be doing an IR drop analysis?

    - Kari 

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