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Problems with synthesis using RTL compiler and PKS

Renee

I used both PKS and RTL compiler to synthesize a verilog file, then used the .v file to do place and route with soc encounter. When I do post-layout simulation, I find that the routing result file using .v file generated by PKS produced the right result, while the one using .v file generated by RTL compiler cannot produce the right result, because the synthesis result from RTL compiler contained:

  assign SelExt = IR[15];
  assign SelV0 = SelC0;
  assign SelZ0 = SelC0;
  assign SelZ = SelC;
  assign SelV = SelC;

Then after routing, when I do extraction, there are only SelZ, SelZ0 and SelExt signals left, while SelC, SelC0, SelV and SelV0 are deleted as being the same nets, so it caused problems of not matching the IO list of the module when I simulate.

 Then I tried with another behavioural design, similarly the routing result using PKS as synthesis tool produced the right result, while the one using RTL compiler failed to pass the simulation. But this time, it did not have the same nets problem, just not being able to produce the right result.

 I don't understand. Is that possible that using PKS and RTL compiler synthesize the same design while the files did not have the same function? Or I made mistakes? (I used the same process to do place and route and except the .v file, the two designs have the same other files)

  Thank you!

 

Parents

  •  Hi Renee,

     

    not sure what you mean by "right" results. As it was already mentioned, assign removal can be handled in a variety of ways. The previous post mentioend the approaches available using Encounter. In RC, you can use remove_assigns and in PKS there is a variable to enable/disable this capability. As per failing gate level simulation, I suggest you use an equivalence checking tools such as Conformal LEC or Formality altough my experience is that Formality is not very good without side files hence has a hard time validating RC netlists. Such tools provide a much more exhaustive and safe way to validate RTL vs. Netlist functionality. Some of the failure on your gate level sims could also be related to timing and not at all with functionality. An EC tool will quicklyl validate that for you. As per PKS and RC behaving differently, there are ultimately different tools hence they could behave differently but neither ones should produce logical bugs.

     

    hope this helps,

    gh-

Reply

  •  Hi Renee,

     

    not sure what you mean by "right" results. As it was already mentioned, assign removal can be handled in a variety of ways. The previous post mentioend the approaches available using Encounter. In RC, you can use remove_assigns and in PKS there is a variable to enable/disable this capability. As per failing gate level simulation, I suggest you use an equivalence checking tools such as Conformal LEC or Formality altough my experience is that Formality is not very good without side files hence has a hard time validating RC netlists. Such tools provide a much more exhaustive and safe way to validate RTL vs. Netlist functionality. Some of the failure on your gate level sims could also be related to timing and not at all with functionality. An EC tool will quicklyl validate that for you. As per PKS and RC behaving differently, there are ultimately different tools hence they could behave differently but neither ones should produce logical bugs.

     

    hope this helps,

    gh-

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