Low-Power Tip of the Week: Using standard logic gates for isolation

As process geometry shrinks, leakage power increases exponentially.  To reduce leakage power, power shutoff (PSO) of inactive blocks is rapidly becoming a design requirement.

When a block shuts off, its outputs must be isolated.  From simulation point of view, outputs of a shut-off block should be driven to X to indicate that the block is not driving valid values.  Isolation keeps the X values of the shutoff block from propagating to the active portion of the chip.  From circuit point of view, isolation prevents a floating output of the shutoff block from turning on both NMOS and PMOS transistors and causing short-circuit current in an active gate.

Some designs have used standard logic gates (AND, OR gates) for isolation.  This is not recommended.  The danger with this approach is that the designer may not be fully aware of how these gates are built.  If this gate has an inverter on the data input, then it could dissipate short-circuit current when the driver of the data input is shut off (floating).

The recommended methodology is to use dedicated isolation cells provided by the library vendor.  These cells have been designed to ensure no short-circuit current when isolation is enabled.

If a designer must use standard logic gates for isolation, he/she must verify the transistor-level schematic to make sure that there are no inverters on the inputs of these gates.  The desginer must also use the “-non_dedicated” option of the define_isolation_cell CPF command to indicate that this gate can be used for both standard logic and for isolation.

One should always use Conform Low Power (CLP) to check the integrity and structure of the low-power circuits.  If standard logic gates are used for isolation, it is even more important to use CLP to check for any sneak-path current.  This ensures that the design will achieve the low-power objectives.

Luke