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  3. avoiding cells with multiple inputs

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avoiding cells with multiple inputs

designer
designer over 16 years ago

Hi All,

When I synthesize a design with RC, it uses some library cells which have multiple inputs (e.g. AND-OR combinations with 4 inputs). When all the inputs are not required, RC connects the unused inputs to constant 0/1. Since these constants are connected to lib cells, they can not be removed by the delete_unloaded_undriven command. On the other hand I don't want to use TiHi/Lo cells for these unused pins. Is there a way to direct the RC to avoid using lib cells with multiple inputs, when all their inputs are not used?

 Thank you in advance,

Masoud 

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  • grasshopper
    grasshopper over 16 years ago

     Hi Masoud,

    as far as I know RC should not waste a larger cell the way you are describing. If RC uses a 3-input OR and one of them is a logic zero, then RC would normally swap it for a a 2-input OR. You may want to take a closer look at the RTL and scripts or post to the Logic Design forum and hope some RC user has the answer for you.

     

    gh-

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  • designer
    designer over 16 years ago
    Hello  gh,

    We checked the netlist and it seems that RC has not done any constant propagation!!?

    We have a module which assigns a constant to the output ports! I expected that RC propagates the constant and remove the output port from this block! But this did not happend!

    When does RC run  the constant propagation? during  " Synthesize -to_generic "or  during "Synthesize -to_map"?

    Is there an attribute that  enables/disables the constant propagation?


    Regards,

    Masoud
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  • grasshopper
    grasshopper over 16 years ago

    Hi Masoud,

    I think the attributes you are looking for are

    optimize_constant_1_flops

    optimize_constant_0_flops

    The rest should be handled by boolean minimization unless some constraint is getting the in the way

    I was just re-reading you email and noticed a couple of things:

    constant prop happens at multiple points in the flow since every optimization enables previous tricks to be run again

    If a constant is tied to an output and the output propagate across the hierarchy, RC will eliminate the wire across the hierarchy and connect it at the load since it would otherwise be a waste of routing resourced. However, what may happen is that your original output connected to constant remains there due to the attribute

    hdl_undriven_output_port_value

    hope this helps,

    gh-

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  • designer
    designer over 16 years ago
    Hi,

    Thanks for the comments! I will check these atrributes.

    Regards,
    Masoud
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