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PAD connections in Encounter

naderi

 Hello everyone, 

I have manually modified synthesized RTL to include pad cells and their connections, then, fed them to Encounter v6.2 for place and route. After place and route, I realized vdd and gnd net are not connected to any pin.

I am wondering if I have to remove pad cells from input RTL.

Also, other IOs are connected to the associated pads by a metal layer that has the minimum width. What is the best way to define width of metal layer for connecting to the pads.

Thanks,

Ali 

Parents

  • Dear all,

     I have a problem. I define in my verilog file Pin and and I/O and connect them together. I define in the abc.io the Pin and Pad,  an d load the design in encounter. The pins a placed but not the Pad due to some errors. 

    Verilog File abc.v:

    module abc(clk, spi_sck_BU12P, spi_sdi_BU12P, spi_sdo_ICP, spi_chip_select_BU12P

    , led_BU12P, switch_ICP, reset_ICP, flash_reset_i_ICP, cc_vreg_en_BU12P

    , cc_reset_BU12P, cc_fifo_ICP, cc_fifop_ICP, cc_cca_ICP, cc_sfd_ICP

    , lcd_d_BBT16P, lcd_rs_BU12P, lcd_rw_BU12P, lcd_e_BU12P);

     

    BU12P spi_chip_select_2_Inst_BU12P(.A(spi_chip_select_pad[2]), .PAD(spi_chip_select_BU12P[2]));

    BU12P spi_chip_select_1_Inst_BU12P(.A(spi_chip_select_pad[1]), .PAD(spi_chip_select_BU12P[1]));

    BU12P spi_chip_select_0_Inst_BU12P(.A(spi_chip_select_pad[0]), .PAD(spi_chip_select_BU12P[0]));

    ICP flash_reset_i_Inst_ICP(.PAD(flash_reset_i_ICP), .Y(flash_reset_i_pad));

     ---------

    -------

    endmodule

     

    Reading IO assignment file "abc.io" ...

    **Warn: ignored IO file "spi_top.io" line 14: Pad: flash_reset_i_Inst_ICP N

    Reason: unable to determine object from name.

    **Warn: ignored IO file "spi_top.io" line 17: Pad: spi_chip_select_0_Inst_BU12P N

    Reason: unable to determine object from name.

    .........

    Can anyone tell what it does mean?

    Thanks,

     

    Eric

     

Reply

  • Dear all,

     I have a problem. I define in my verilog file Pin and and I/O and connect them together. I define in the abc.io the Pin and Pad,  an d load the design in encounter. The pins a placed but not the Pad due to some errors. 

    Verilog File abc.v:

    module abc(clk, spi_sck_BU12P, spi_sdi_BU12P, spi_sdo_ICP, spi_chip_select_BU12P

    , led_BU12P, switch_ICP, reset_ICP, flash_reset_i_ICP, cc_vreg_en_BU12P

    , cc_reset_BU12P, cc_fifo_ICP, cc_fifop_ICP, cc_cca_ICP, cc_sfd_ICP

    , lcd_d_BBT16P, lcd_rs_BU12P, lcd_rw_BU12P, lcd_e_BU12P);

     

    BU12P spi_chip_select_2_Inst_BU12P(.A(spi_chip_select_pad[2]), .PAD(spi_chip_select_BU12P[2]));

    BU12P spi_chip_select_1_Inst_BU12P(.A(spi_chip_select_pad[1]), .PAD(spi_chip_select_BU12P[1]));

    BU12P spi_chip_select_0_Inst_BU12P(.A(spi_chip_select_pad[0]), .PAD(spi_chip_select_BU12P[0]));

    ICP flash_reset_i_Inst_ICP(.PAD(flash_reset_i_ICP), .Y(flash_reset_i_pad));

     ---------

    -------

    endmodule

     

    Reading IO assignment file "abc.io" ...

    **Warn: ignored IO file "spi_top.io" line 14: Pad: flash_reset_i_Inst_ICP N

    Reason: unable to determine object from name.

    **Warn: ignored IO file "spi_top.io" line 17: Pad: spi_chip_select_0_Inst_BU12P N

    Reason: unable to determine object from name.

    .........

    Can anyone tell what it does mean?

    Thanks,

     

    Eric

     

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