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Few queries about Max Dynamic power estimation

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I always wonder about how does designer cares about instantaneous peak power while desgining power grid. As we know the instantaneous dynamic power is directly proportional to switching activity at any instant in a design and finding out the Max switching activity is an NP Complete problem.Therefore peak power values seems to me a big gray area for a designer and brings about certain questions in my mind 1) How does designer sign off the power grid design in today's world without having the knowledge of accurate peak power or atleast a stricter upper bound on peak power values. 2) Are there any commercial tools which attempt to solve accurate peak dynamic power estimation problem both in functional as well test mode. 3) I see this as big issue as the technology further shrinks.How is EDA/semiconductor industry is planning to tackle this problem. Looking forward for replies from both designers and EDA experts. Thanks and regds Mudit


Originally posted in cdnusers.org by mudits
Parents

  • Mudit,

    You have raised some great questions. Power estimation and analysis is a complex topic but has huge implications. Under estimation of power will cause chip failure on the tester or in the system. Over estimation of power will be costly due to larger die size, more expensive package, and greater system cooling requirement.

    As you have correctly pointed out, switching activity is a is a key component of dynamic power. Most designers try to get switching activity from simulation. The problem here is that most testbenches are written to detect design errors and may not reflect actual chip operation. Even if tests are written to simulation real-life operation, the simulation may take too long to reach the peak activity period. As a result, you might get local rather than global peak power.

    Many designers estimate power dissipation with a combination of switching activity from simulation, measured power dissipation from previous designs, and some sort of power margin (fudge factor) to account for uncertainty.

    Regardless of which method you use to estimate power, it is important to do it early in the design cycle so that you have the power architecture to meet your power requirements. Failure to meet the power requirement late in the design cycle is a sure way to blow the project schedule.

    Does anyone else have any comments?

    Luke Lang


    Originally posted in cdnusers.org by lukelang
Reply

  • Mudit,

    You have raised some great questions. Power estimation and analysis is a complex topic but has huge implications. Under estimation of power will cause chip failure on the tester or in the system. Over estimation of power will be costly due to larger die size, more expensive package, and greater system cooling requirement.

    As you have correctly pointed out, switching activity is a is a key component of dynamic power. Most designers try to get switching activity from simulation. The problem here is that most testbenches are written to detect design errors and may not reflect actual chip operation. Even if tests are written to simulation real-life operation, the simulation may take too long to reach the peak activity period. As a result, you might get local rather than global peak power.

    Many designers estimate power dissipation with a combination of switching activity from simulation, measured power dissipation from previous designs, and some sort of power margin (fudge factor) to account for uncertainty.

    Regardless of which method you use to estimate power, it is important to do it early in the design cycle so that you have the power architecture to meet your power requirements. Failure to meet the power requirement late in the design cycle is a sure way to blow the project schedule.

    Does anyone else have any comments?

    Luke Lang


    Originally posted in cdnusers.org by lukelang
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