• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Digital Implementation
  3. Estimated power consumption of a full custom digital IC...

Stats

  • Locked Locked
  • Replies 2
  • Subscribers 90
  • Views 13701
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Estimated power consumption of a full custom digital IC design

archive
archive over 17 years ago

I have drawn a full custom digital circuit using Cadence Virtuoso and have simulated it using Spectre. I wish to obtain the dynamic (including both switching and short-circuit) and leakage power components of the circuit. How do I estimate it for a given set of input stimuli. I also like to know as to how do I get to know the worst case delay of the circuit, for rising and falling transitions separately? Expecting your clear replies as I am quite new to full custom digital IC design.

Thanks,
Bala


Originally posted in cdnusers.org by spbalan04
  • Cancel
  • archive
    archive over 17 years ago

    Bala,

    Your question is broad and covers a series of tools. A lot more detail is needed to properly answer your question. In general, the flow can be split into the following parts:

    1. Extraction (QRC)
    2. Simulation (Sprectre, Ultrasim)
    3. Analysis (VoltageStore - IR/EM analysis)
    4. Litho effect on manufacturability and timing, if 65 nm or below.

    The best way to obtain support is to file a Service Request with Cadence or talk to your Cadence Account Executive. The solution that you are looking for cannot be adequately addressed in this forum.

    Luke Lang


    Originally posted in cdnusers.org by lukelang
    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • archive
    archive over 17 years ago

    After drawing the transistor level schematic using Cadence Virtuoso and subsequent simulation using Spectre, I was able to see the current waveform. When I used Wavescan on the netlist (transistor level SPICE like netlist), I was able to see the power consumption in microWatts. But there were two power values. One, I think corresponds to the current flow when the circuit turned ON multiplied by the supply voltage. I think this might be the dynamic power component. Apart from this, there was another power component. I don't know whether this refers to the total power consumption as it was higher than the dynamic component. Could you kindly clarify? I haven't extracted the layout and the above figures are obtained before getting the layout.

    Thanks,
    Bala


    Originally posted in cdnusers.org by spbalan04
    • Cancel
    • Vote Up 0 Vote Down
    • Cancel

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information