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Cell delay estimation for pre route and post route

gops
How does the encounter estimates cell delay for post route and pre routes. Actually my doubt is about the load capacitance it will take for both the analysis.I think that for pre route it takes the load capacitance as the sum of both net capacitance(in the WLM) and pin capacitance of the driven cell.But for post route which load cpacitance its going to take.Is it the same as pre route OR is it the effective capacitance as seen from the driving pin?
Parents
  • Hi BobD ;
    Thanks for your reply.I'm a beginner in ASIC design.So i may be wrong sometimes.Anyway i shall tell you my exact problem in a detailed way.
    from your reply i understood that Encounter does not take wireload models for delay calculation.ok thats fine. Then it may be taking the extracted prasitics of trial route during pre route and nanoroute during post route.
     
    I'm having the idea that ;
     
    For calculating the delay for a cell two things are considered
    1) input slew
    2) output load.
     
    In the sdf file , i have seen both interconnect delay as well as cell delay. You told that the extracted net parasitic will be added to the input pin cap of driven cell to calculate cell delay. So it means that you have already considered the delay of the interconnect to calculate cell delay , is'nt it?If thats the case what is the need of calculating the interconnect delay once more?
Reply
  • Hi BobD ;
    Thanks for your reply.I'm a beginner in ASIC design.So i may be wrong sometimes.Anyway i shall tell you my exact problem in a detailed way.
    from your reply i understood that Encounter does not take wireload models for delay calculation.ok thats fine. Then it may be taking the extracted prasitics of trial route during pre route and nanoroute during post route.
     
    I'm having the idea that ;
     
    For calculating the delay for a cell two things are considered
    1) input slew
    2) output load.
     
    In the sdf file , i have seen both interconnect delay as well as cell delay. You told that the extracted net parasitic will be added to the input pin cap of driven cell to calculate cell delay. So it means that you have already considered the delay of the interconnect to calculate cell delay , is'nt it?If thats the case what is the need of calculating the interconnect delay once more?
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