• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Digital Implementation
  3. sdf backannotation

Stats

  • Locked Locked
  • Replies 4
  • Subscribers 92
  • Views 13739
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

sdf backannotation

gops
gops over 16 years ago
I have generated the netlist(verilog) and sdf file from Encounter.Now i need to simulate the netlist in nclaunch.Can any one please tell what are the library files required for the purpose. I have vital libraries with me , but they are of .vhd extension. Can i use those vital libraris for simulating verilog netlist OR do i need to procure any verilog libraries for the same?
  • Cancel
  • Mickey
    Mickey over 16 years ago
    Although you can use the vhdl library, it would be best to obtain and use a verilog version of the library cells. This is because there could be a large performance impact due to having to transition through the language boundary for every cell.  The library would be something provided by the vendor whose cells are being used.
     
    Since you already have VHDL libraries, another method could be to have the netlist created in VHDL.
     

    Let me know if this helps.

    Best regards,
    Mickey
    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • gops
    gops over 16 years ago
    Hi Mickey;

    thanks for the reply.

    You told to create the netlist in VHDL.

    But i think its not possible to generate VHDL netlist from encounter.Isn't it ?

    thanks
    gops
    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • Mickey
    Mickey over 16 years ago

    Hi Gops,

    Unfortunately I missed the indication that you are using Encounter.  With that in mind it would be good to use a verilog version of the cell library.  You can still use the VHDL library if you don't have a verilog version, but there will more than likely be a performance impact due to the large number of language boundary crossings that can be forseen in such a situation.

    Best regards,
    Mickey

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • gops
    gops over 16 years ago
    Hi Mickey;
     
    thanks for the reply.
     
    gops.
    • Cancel
    • Vote Up 0 Vote Down
    • Cancel

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information